arch/arm/mach-at91/at91sam9263.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9263.c
   3  *
   4  *  Copyright (C) 2007 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/at91sam9263.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_rstc.h>
  22
  23 #include "soc.h"
  24 #include "generic.h"
  25 #include "clock.h"
  26 #include "sam9_smc.h"
  27
  28 /* --------------------------------------------------------------------
  29  *  Clocks
  30  * -------------------------------------------------------------------- */
  31
  32 /*
  33  * The peripheral clocks.
  34  */
  35 static struct clk pioA_clk = {
  36         .name           = "pioA_clk",
  37         .pmc_mask       = 1 << AT91SAM9263_ID_PIOA,
  38         .type           = CLK_TYPE_PERIPHERAL,
  39 };
  40 static struct clk pioB_clk = {
  41         .name           = "pioB_clk",
  42         .pmc_mask       = 1 << AT91SAM9263_ID_PIOB,
  43         .type           = CLK_TYPE_PERIPHERAL,
  44 };
  45 static struct clk pioCDE_clk = {
  46         .name           = "pioCDE_clk",
  47         .pmc_mask       = 1 << AT91SAM9263_ID_PIOCDE,
  48         .type           = CLK_TYPE_PERIPHERAL,
  49 };
  50 static struct clk usart0_clk = {
  51         .name           = "usart0_clk",
  52         .pmc_mask       = 1 << AT91SAM9263_ID_US0,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk usart1_clk = {
  56         .name           = "usart1_clk",
  57         .pmc_mask       = 1 << AT91SAM9263_ID_US1,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60 static struct clk usart2_clk = {
  61         .name           = "usart2_clk",
  62         .pmc_mask       = 1 << AT91SAM9263_ID_US2,
  63         .type           = CLK_TYPE_PERIPHERAL,
  64 };
  65 static struct clk mmc0_clk = {
  66         .name           = "mci0_clk",
  67         .pmc_mask       = 1 << AT91SAM9263_ID_MCI0,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk mmc1_clk = {
  71         .name           = "mci1_clk",
  72         .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk can_clk = {
  76         .name           = "can_clk",
  77         .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk twi_clk = {
  81         .name           = "twi_clk",
  82         .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk spi0_clk = {
  86         .name           = "spi0_clk",
  87         .pmc_mask       = 1 << AT91SAM9263_ID_SPI0,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk spi1_clk = {
  91         .name           = "spi1_clk",
  92         .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk ssc0_clk = {
  96         .name           = "ssc0_clk",
  97         .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk ssc1_clk = {
 101         .name           = "ssc1_clk",
 102         .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk ac97_clk = {
 106         .name           = "ac97_clk",
 107         .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk tcb_clk = {
 111         .name           = "tcb_clk",
 112         .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk pwm_clk = {
 116         .name           = "pwm_clk",
 117         .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk macb_clk = {
 121         .name           = "pclk",
 122         .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk dma_clk = {
 126         .name           = "dma_clk",
 127         .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk twodge_clk = {
 131         .name           = "2dge_clk",
 132         .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135 static struct clk udc_clk = {
 136         .name           = "udc_clk",
 137         .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
 138         .type           = CLK_TYPE_PERIPHERAL,
 139 };
 140 static struct clk isi_clk = {
 141         .name           = "isi_clk",
 142         .pmc_mask       = 1 << AT91SAM9263_ID_ISI,
 143         .type           = CLK_TYPE_PERIPHERAL,
 144 };
 145 static struct clk lcdc_clk = {
 146         .name           = "lcdc_clk",
 147         .pmc_mask       = 1 << AT91SAM9263_ID_LCDC,
 148         .type           = CLK_TYPE_PERIPHERAL,
 149 };
 150 static struct clk ohci_clk = {
 151         .name           = "ohci_clk",
 152         .pmc_mask       = 1 << AT91SAM9263_ID_UHP,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155
 156 static struct clk *periph_clocks[] __initdata = {
 157         &pioA_clk,
 158         &pioB_clk,
 159         &pioCDE_clk,
 160         &usart0_clk,
 161         &usart1_clk,
 162         &usart2_clk,
 163         &mmc0_clk,
 164         &mmc1_clk,
 165         &can_clk,
 166         &twi_clk,
 167         &spi0_clk,
 168         &spi1_clk,
 169         &ssc0_clk,
 170         &ssc1_clk,
 171         &ac97_clk,
 172         &tcb_clk,
 173         &pwm_clk,
 174         &macb_clk,
 175         &twodge_clk,
 176         &udc_clk,
 177         &isi_clk,
 178         &lcdc_clk,
 179         &dma_clk,
 180         &ohci_clk,
 181         // irq0 .. irq1
 182 };
 183
 184 static struct clk_lookup periph_clocks_lookups[] = {
 185         /* One additional fake clock for macb_hclk */
 186         CLKDEV_CON_ID("hclk", &macb_clk),
 187         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 188         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 189         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
 190         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
 191         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 192         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 193         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
 194         /* fake hclk clock */
 195         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 196         CLKDEV_CON_ID("pioA", &pioA_clk),
 197         CLKDEV_CON_ID("pioB", &pioB_clk),
 198         CLKDEV_CON_ID("pioC", &pioCDE_clk),
 199         CLKDEV_CON_ID("pioD", &pioCDE_clk),
 200         CLKDEV_CON_ID("pioE", &pioCDE_clk),
 201 };
 202
 203 static struct clk_lookup usart_clocks_lookups[] = {
 204         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 205         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 206         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 207         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 208 };
 209
 210 /*
 211  * The four programmable clocks.
 212  * You must configure pin multiplexing to bring these signals out.
 213  */
 214 static struct clk pck0 = {
 215         .name           = "pck0",
 216         .pmc_mask       = AT91_PMC_PCK0,
 217         .type           = CLK_TYPE_PROGRAMMABLE,
 218         .id             = 0,
 219 };
 220 static struct clk pck1 = {
 221         .name           = "pck1",
 222         .pmc_mask       = AT91_PMC_PCK1,
 223         .type           = CLK_TYPE_PROGRAMMABLE,
 224         .id             = 1,
 225 };
 226 static struct clk pck2 = {
 227         .name           = "pck2",
 228         .pmc_mask       = AT91_PMC_PCK2,
 229         .type           = CLK_TYPE_PROGRAMMABLE,
 230         .id             = 2,
 231 };
 232 static struct clk pck3 = {
 233         .name           = "pck3",
 234         .pmc_mask       = AT91_PMC_PCK3,
 235         .type           = CLK_TYPE_PROGRAMMABLE,
 236         .id             = 3,
 237 };
 238
 239 static void __init at91sam9263_register_clocks(void)
 240 {
 241         int i;
 242
 243         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 244                 clk_register(periph_clocks[i]);
 245
 246         clkdev_add_table(periph_clocks_lookups,
 247                          ARRAY_SIZE(periph_clocks_lookups));
 248         clkdev_add_table(usart_clocks_lookups,
 249                          ARRAY_SIZE(usart_clocks_lookups));
 250
 251         clk_register(&pck0);
 252         clk_register(&pck1);
 253         clk_register(&pck2);
 254         clk_register(&pck3);
 255 }
 256
 257 static struct clk_lookup console_clock_lookup;
 258
 259 void __init at91sam9263_set_console_clock(int id)
 260 {
 261         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 262                 return;
 263
 264         console_clock_lookup.con_id = "usart";
 265         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 266         clkdev_add(&console_clock_lookup);
 267 }
 268
 269 /* --------------------------------------------------------------------
 270  *  GPIO
 271  * -------------------------------------------------------------------- */
 272
 273 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
 274         {
 275                 .id             = AT91SAM9263_ID_PIOA,
 276                 .regbase        = AT91SAM9263_BASE_PIOA,
 277         }, {
 278                 .id             = AT91SAM9263_ID_PIOB,
 279                 .regbase        = AT91SAM9263_BASE_PIOB,
 280         }, {
 281                 .id             = AT91SAM9263_ID_PIOCDE,
 282                 .regbase        = AT91SAM9263_BASE_PIOC,
 283         }, {
 284                 .id             = AT91SAM9263_ID_PIOCDE,
 285                 .regbase        = AT91SAM9263_BASE_PIOD,
 286         }, {
 287                 .id             = AT91SAM9263_ID_PIOCDE,
 288                 .regbase        = AT91SAM9263_BASE_PIOE,
 289         }
 290 };
 291
 292 /* --------------------------------------------------------------------
 293  *  AT91SAM9263 processor initialization
 294  * -------------------------------------------------------------------- */
 295
 296 static void __init at91sam9263_map_io(void)
 297 {
 298         at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
 299         at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
 300 }
 301
 302 static void __init at91sam9263_ioremap_registers(void)
 303 {
 304         at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
 305         at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
 306         at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
 307         at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
 308         at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
 309         at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
 310         at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
 311         at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
 312 }
 313
 314 static void __init at91sam9263_initialize(void)
 315 {
 316         arm_pm_idle = at91sam9_idle;
 317         arm_pm_restart = at91sam9_alt_restart;
 318         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 319
 320         /* Register GPIO subsystem */
 321         at91_gpio_init(at91sam9263_gpio, 5);
 322 }
 323
 324 /* --------------------------------------------------------------------
 325  *  Interrupt initialization
 326  * -------------------------------------------------------------------- */
 327
 328 /*
 329  * The default interrupt priority levels (0 = lowest, 7 = highest).
 330  */
 331 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 332         7,      /* Advanced Interrupt Controller (FIQ) */
 333         7,      /* System Peripherals */
 334         1,      /* Parallel IO Controller A */
 335         1,      /* Parallel IO Controller B */
 336         1,      /* Parallel IO Controller C, D and E */
 337         0,
 338         0,
 339         5,      /* USART 0 */
 340         5,      /* USART 1 */
 341         5,      /* USART 2 */
 342         0,      /* Multimedia Card Interface 0 */
 343         0,      /* Multimedia Card Interface 1 */
 344         3,      /* CAN */
 345         6,      /* Two-Wire Interface */
 346         5,      /* Serial Peripheral Interface 0 */
 347         5,      /* Serial Peripheral Interface 1 */
 348         4,      /* Serial Synchronous Controller 0 */
 349         4,      /* Serial Synchronous Controller 1 */
 350         5,      /* AC97 Controller */
 351         0,      /* Timer Counter 0, 1 and 2 */
 352         0,      /* Pulse Width Modulation Controller */
 353         3,      /* Ethernet */
 354         0,
 355         0,      /* 2D Graphic Engine */
 356         2,      /* USB Device Port */
 357         0,      /* Image Sensor Interface */
 358         3,      /* LDC Controller */
 359         0,      /* DMA Controller */
 360         0,
 361         2,      /* USB Host port */
 362         0,      /* Advanced Interrupt Controller (IRQ0) */
 363         0,      /* Advanced Interrupt Controller (IRQ1) */
 364 };
 365
 366 struct at91_init_soc __initdata at91sam9263_soc = {
 367         .map_io = at91sam9263_map_io,
 368         .default_irq_priority = at91sam9263_default_irq_priority,
 369         .ioremap_registers = at91sam9263_ioremap_registers,
 370         .register_clocks = at91sam9263_register_clocks,
 371         .init = at91sam9263_initialize,
 372 };