arch/arm/mach-apple/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <efi_loader.h>
   9 #include <lmb.h>
  10
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/system.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 /* Apple M1 */
  19
  20 static struct mm_region t8103_mem_map[] = {
  21         {
  22                 /* I/O */
  23                 .virt = 0x200000000,
  24                 .phys = 0x200000000,
  25                 .size = 2UL * SZ_1G,
  26                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  27                          PTE_BLOCK_NON_SHARE |
  28                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  29         }, {
  30                 /* I/O */
  31                 .virt = 0x380000000,
  32                 .phys = 0x380000000,
  33                 .size = SZ_1G,
  34                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  35                          PTE_BLOCK_NON_SHARE |
  36                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  37         }, {
  38                 /* I/O */
  39                 .virt = 0x500000000,
  40                 .phys = 0x500000000,
  41                 .size = SZ_1G,
  42                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  43                          PTE_BLOCK_NON_SHARE |
  44                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  45         }, {
  46                 /* I/O */
  47                 .virt = 0x680000000,
  48                 .phys = 0x680000000,
  49                 .size = SZ_512M,
  50                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  51                          PTE_BLOCK_NON_SHARE |
  52                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  53         }, {
  54                 /* PCIE */
  55                 .virt = 0x6a0000000,
  56                 .phys = 0x6a0000000,
  57                 .size = SZ_512M,
  58                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
  59                          PTE_BLOCK_INNER_SHARE |
  60                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  61         }, {
  62                 /* PCIE */
  63                 .virt = 0x6c0000000,
  64                 .phys = 0x6c0000000,
  65                 .size = SZ_1G,
  66                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
  67                          PTE_BLOCK_INNER_SHARE |
  68                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  69         }, {
  70                 /* RAM */
  71                 .virt = 0x800000000,
  72                 .phys = 0x800000000,
  73                 .size = 8UL * SZ_1G,
  74                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  75                          PTE_BLOCK_INNER_SHARE
  76         }, {
  77                 /* Framebuffer */
  78                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  79                          PTE_BLOCK_INNER_SHARE |
  80                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  81         }, {
  82                 /* List terminator */
  83                 0,
  84         }
  85 };
  86
  87 /* Apple M1 Pro/Max */
  88
  89 static struct mm_region t6000_mem_map[] = {
  90         {
  91                 /* I/O */
  92                 .virt = 0x280000000,
  93                 .phys = 0x280000000,
  94                 .size = SZ_1G,
  95                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  96                          PTE_BLOCK_NON_SHARE |
  97                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  98         }, {
  99                 /* I/O */
 100                 .virt = 0x380000000,
 101                 .phys = 0x380000000,
 102                 .size = SZ_1G,
 103                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 104                          PTE_BLOCK_NON_SHARE |
 105                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 106         }, {
 107                 /* I/O */
 108                 .virt = 0x580000000,
 109                 .phys = 0x580000000,
 110                 .size = SZ_512M,
 111                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 112                          PTE_BLOCK_NON_SHARE |
 113                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 114         }, {
 115                 /* PCIE */
 116                 .virt = 0x5a0000000,
 117                 .phys = 0x5a0000000,
 118                 .size = SZ_512M,
 119                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
 120                          PTE_BLOCK_INNER_SHARE |
 121                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 122         }, {
 123                 /* PCIE */
 124                 .virt = 0x5c0000000,
 125                 .phys = 0x5c0000000,
 126                 .size = SZ_1G,
 127                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
 128                          PTE_BLOCK_INNER_SHARE |
 129                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 130         }, {
 131                 /* I/O */
 132                 .virt = 0x700000000,
 133                 .phys = 0x700000000,
 134                 .size = SZ_1G,
 135                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 136                          PTE_BLOCK_NON_SHARE |
 137                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 138         }, {
 139                 /* I/O */
 140                 .virt = 0xb00000000,
 141                 .phys = 0xb00000000,
 142                 .size = SZ_1G,
 143                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 144                          PTE_BLOCK_NON_SHARE |
 145                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 146         }, {
 147                 /* I/O */
 148                 .virt = 0xf00000000,
 149                 .phys = 0xf00000000,
 150                 .size = SZ_1G,
 151                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 152                          PTE_BLOCK_NON_SHARE |
 153                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 154         }, {
 155                 /* I/O */
 156                 .virt = 0x1300000000,
 157                 .phys = 0x1300000000,
 158                 .size = SZ_1G,
 159                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 160                          PTE_BLOCK_NON_SHARE |
 161                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 162         }, {
 163                 /* RAM */
 164                 .virt = 0x10000000000,
 165                 .phys = 0x10000000000,
 166                 .size = 16UL * SZ_1G,
 167                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 168                          PTE_BLOCK_INNER_SHARE
 169         }, {
 170                 /* Framebuffer */
 171                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
 172                          PTE_BLOCK_INNER_SHARE |
 173                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 174         }, {
 175                 /* List terminator */
 176                 0,
 177         }
 178 };
 179
 180 /* Apple M1 Ultra */
 181
 182 static struct mm_region t6002_mem_map[] = {
 183         {
 184                 /* I/O */
 185                 .virt = 0x280000000,
 186                 .phys = 0x280000000,
 187                 .size = SZ_1G,
 188                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 189                          PTE_BLOCK_NON_SHARE |
 190                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 191         }, {
 192                 /* I/O */
 193                 .virt = 0x380000000,
 194                 .phys = 0x380000000,
 195                 .size = SZ_1G,
 196                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 197                          PTE_BLOCK_NON_SHARE |
 198                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 199         }, {
 200                 /* I/O */
 201                 .virt = 0x580000000,
 202                 .phys = 0x580000000,
 203                 .size = SZ_512M,
 204                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 205                          PTE_BLOCK_NON_SHARE |
 206                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 207         }, {
 208                 /* PCIE */
 209                 .virt = 0x5a0000000,
 210                 .phys = 0x5a0000000,
 211                 .size = SZ_512M,
 212                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
 213                          PTE_BLOCK_INNER_SHARE |
 214                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 215         }, {
 216                 /* PCIE */
 217                 .virt = 0x5c0000000,
 218                 .phys = 0x5c0000000,
 219                 .size = SZ_1G,
 220                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
 221                          PTE_BLOCK_INNER_SHARE |
 222                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 223         }, {
 224                 /* I/O */
 225                 .virt = 0x700000000,
 226                 .phys = 0x700000000,
 227                 .size = SZ_1G,
 228                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 229                          PTE_BLOCK_NON_SHARE |
 230                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 231         }, {
 232                 /* I/O */
 233                 .virt = 0xb00000000,
 234                 .phys = 0xb00000000,
 235                 .size = SZ_1G,
 236                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 237                          PTE_BLOCK_NON_SHARE |
 238                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 239         }, {
 240                 /* I/O */
 241                 .virt = 0xf00000000,
 242                 .phys = 0xf00000000,
 243                 .size = SZ_1G,
 244                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 245                          PTE_BLOCK_NON_SHARE |
 246                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 247         }, {
 248                 /* I/O */
 249                 .virt = 0x1300000000,
 250                 .phys = 0x1300000000,
 251                 .size = SZ_1G,
 252                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 253                          PTE_BLOCK_NON_SHARE |
 254                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 255         }, {
 256                 /* I/O */
 257                 .virt = 0x2280000000,
 258                 .phys = 0x2280000000,
 259                 .size = SZ_1G,
 260                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 261                          PTE_BLOCK_NON_SHARE |
 262                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 263         }, {
 264                 /* I/O */
 265                 .virt = 0x2380000000,
 266                 .phys = 0x2380000000,
 267                 .size = SZ_1G,
 268                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 269                          PTE_BLOCK_NON_SHARE |
 270                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 271         }, {
 272                 /* I/O */
 273                 .virt = 0x2580000000,
 274                 .phys = 0x2580000000,
 275                 .size = SZ_512M,
 276                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 277                          PTE_BLOCK_NON_SHARE |
 278                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 279         }, {
 280                 /* PCIE */
 281                 .virt = 0x25a0000000,
 282                 .phys = 0x25a0000000,
 283                 .size = SZ_512M,
 284                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
 285                          PTE_BLOCK_INNER_SHARE |
 286                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 287         }, {
 288                 /* PCIE */
 289                 .virt = 0x25c0000000,
 290                 .phys = 0x25c0000000,
 291                 .size = SZ_1G,
 292                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
 293                          PTE_BLOCK_INNER_SHARE |
 294                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 295         }, {
 296                 /* I/O */
 297                 .virt = 0x2700000000,
 298                 .phys = 0x2700000000,
 299                 .size = SZ_1G,
 300                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 301                          PTE_BLOCK_NON_SHARE |
 302                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 303         }, {
 304                 /* I/O */
 305                 .virt = 0x2b00000000,
 306                 .phys = 0x2b00000000,
 307                 .size = SZ_1G,
 308                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 309                          PTE_BLOCK_NON_SHARE |
 310                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 311         }, {
 312                 /* I/O */
 313                 .virt = 0x2f00000000,
 314                 .phys = 0x2f00000000,
 315                 .size = SZ_1G,
 316                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 317                          PTE_BLOCK_NON_SHARE |
 318                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 319         }, {
 320                 /* I/O */
 321                 .virt = 0x3300000000,
 322                 .phys = 0x3300000000,
 323                 .size = SZ_1G,
 324                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 325                          PTE_BLOCK_NON_SHARE |
 326                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 327         }, {
 328                 /* RAM */
 329                 .virt = 0x10000000000,
 330                 .phys = 0x10000000000,
 331                 .size = 16UL * SZ_1G,
 332                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 333                          PTE_BLOCK_INNER_SHARE
 334         }, {
 335                 /* Framebuffer */
 336                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
 337                          PTE_BLOCK_INNER_SHARE |
 338                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 339         }, {
 340                 /* List terminator */
 341                 0,
 342         }
 343 };
 344
 345 struct mm_region *mem_map;
 346
 347 int board_init(void)
 348 {
 349         return 0;
 350 }
 351
 352 int dram_init(void)
 353 {
 354         return fdtdec_setup_mem_size_base();
 355 }
 356
 357 int dram_init_banksize(void)
 358 {
 359         return fdtdec_setup_memory_banksize();
 360 }
 361
 362 extern long fw_dtb_pointer;
 363
 364 void *board_fdt_blob_setup(int *err)
 365 {
 366         /* Return DTB pointer passed by m1n1 */
 367         *err = 0;
 368         return (void *)fw_dtb_pointer;
 369 }
 370
 371 void build_mem_map(void)
 372 {
 373         ofnode node;
 374         fdt_addr_t base;
 375         fdt_size_t size;
 376         int i;
 377
 378         if (of_machine_is_compatible("apple,t8103"))
 379                 mem_map = t8103_mem_map;
 380         else if (of_machine_is_compatible("apple,t6000"))
 381                 mem_map = t6000_mem_map;
 382         else if (of_machine_is_compatible("apple,t6001"))
 383                 mem_map = t6000_mem_map;
 384         else if (of_machine_is_compatible("apple,t6002"))
 385                 mem_map = t6002_mem_map;
 386         else
 387                 panic("Unsupported SoC\n");
 388
 389         /* Find list terminator. */
 390         for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
 391                 ;
 392
 393         /* Align RAM mapping to page boundaries */
 394         base = gd->bd->bi_dram[0].start;
 395         size = gd->bd->bi_dram[0].size;
 396         size += (base - ALIGN_DOWN(base, SZ_4K));
 397         base = ALIGN_DOWN(base, SZ_4K);
 398         size = ALIGN(size, SZ_4K);
 399
 400         /* Update RAM mapping */
 401         mem_map[i - 2].virt = base;
 402         mem_map[i - 2].phys = base;
 403         mem_map[i - 2].size = size;
 404
 405         node = ofnode_path("/chosen/framebuffer");
 406         if (!ofnode_valid(node))
 407                 return;
 408
 409         base = ofnode_get_addr_size(node, "reg", &size);
 410         if (base == FDT_ADDR_T_NONE)
 411                 return;
 412
 413         /* Align framebuffer mapping to page boundaries */
 414         size += (base - ALIGN_DOWN(base, SZ_4K));
 415         base = ALIGN_DOWN(base, SZ_4K);
 416         size = ALIGN(size, SZ_4K);
 417
 418         /* Add framebuffer mapping */
 419         mem_map[i - 1].virt = base;
 420         mem_map[i - 1].phys = base;
 421         mem_map[i - 1].size = size;
 422 }
 423
 424 void enable_caches(void)
 425 {
 426         build_mem_map();
 427
 428         icache_enable();
 429         dcache_enable();
 430 }
 431
 432 u64 get_page_table_size(void)
 433 {
 434         return SZ_256K;
 435 }
 436
 437 #define KERNEL_COMP_SIZE        SZ_128M
 438
 439 int board_late_init(void)
 440 {
 441         struct lmb lmb;
 442         u32 status = 0;
 443
 444         lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
 445
 446         /* somewhat based on the Linux Kernel boot requirements:
 447          * align by 2M and maximal FDT size 2M
 448          */
 449         status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M));
 450         status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M));
 451         status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M));
 452         status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M));
 453         status |= env_set_hex("kernel_comp_addr_r",
 454                               lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M));
 455         status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
 456         status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M));
 457         status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M));
 458
 459         if (status)
 460                 log_warning("late_init: Failed to set run time variables\n");
 461
 462         return 0;
 463 }