1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * GIC Initialization Routines.
6 * David Feng <fenghua@phytium.com.cn>
9 #include <asm-offsets.h>
11 #include <linux/linkage.h>
13 #include <asm/macro.h>
16 /*************************************************************************
18 * void gic_init_secure(DistributorBase);
20 * Initialize secure copy of GIC at EL3.
22 *************************************************************************/
23 ENTRY(gic_init_secure)
25 * Initialize Distributor
26 * x0: Distributor Base
28 #if defined(CONFIG_GICV3)
29 mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */
30 /* EnableGrp1S | ARE_S | ARE_NS */
31 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
32 ldr w9, [x0, GICD_TYPER]
33 and w10, w9, #0x1f /* ITLinesNumber */
34 cbz w10, 1f /* No SPIs */
35 add x11, x0, (GICD_IGROUPRn + 4)
36 add x12, x0, (GICD_IGROUPMODRn + 4)
38 0: str w9, [x11], #0x4
39 str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
42 #elif defined(CONFIG_GICV2)
43 switch_el x1, 2f, 1f, 1f
45 mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
46 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
47 ldr w9, [x0, GICD_TYPER]
48 and w10, w9, #0x1f /* ITLinesNumber */
49 cbz w10, 1f /* No SPIs */
50 add x11, x0, GICD_IGROUPRn
51 mov w9, #~0 /* Config SPIs as Grp1 */
53 0: str w9, [x11], #0x4
57 ldr x1, =GICC_BASE /* GICC_CTLR */
58 mov w0, #3 /* EnableGrp0 | EnableGrp1 */
61 mov w0, #1 << 7 /* allow NS access to GICC_PMR */
62 str w0, [x1, #4] /* GICC_PMR */
66 ENDPROC(gic_init_secure)
69 /*************************************************************************
71 * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
73 * void gic_init_secure_percpu(ReDistributorBase);
75 * Initialize secure copy of GIC at EL3.
77 *************************************************************************/
78 ENTRY(gic_init_secure_percpu)
79 #if defined(CONFIG_GICV3)
81 * Initialize ReDistributor
82 * x0: ReDistributor Base
86 bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
88 1: ldr x11, [x9, GICR_TYPER]
89 lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
92 add x9, x9, #(2 << 16)
95 /* x9: ReDistributor Base Address of Current CPU */
97 ldr w11, [x9, GICR_WAKER]
98 and w11, w11, w10 /* Clear ProcessorSleep */
99 str w11, [x9, GICR_WAKER]
102 3: ldr w10, [x9, GICR_WAKER]
103 tbnz w10, #2, 3b /* Wait Children be Alive */
105 add x10, x9, #(1 << 16) /* SGI_Base */
107 str w11, [x10, GICR_IGROUPRn]
108 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
109 mov w11, #0x1 /* Enable SGI 0 */
110 str w11, [x10, GICR_ISENABLERn]
112 switch_el x10, 3f, 2f, 1f
114 /* Initialize Cpu Interface */
116 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
117 /* Allow EL2 access to ICC_SRE_EL2 */
121 mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
122 msr ICC_IGRPEN1_EL3, x10
125 msr ICC_CTLR_EL3, xzr
129 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
130 /* Allow EL1 access to ICC_SRE_EL1 */
134 msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
137 mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
140 #elif defined(CONFIG_GICV2)
142 * Initialize SGIs and PPIs
143 * x0: Distributor Base
144 * x1: Cpu Interface Base
146 switch_el x2, 4f, 5f, 5f
148 mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
149 str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
150 mov w9, #0x1 /* Enable SGI 0 */
151 str w9, [x0, GICD_ISENABLERn]
153 /* Initialize Cpu Interface */
154 mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
155 /* Enable Ack Group1 Interrupt & */
156 /* EnableGrp0 & EnableGrp1 */
157 str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
159 mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
160 str w9, [x1, GICC_PMR]
164 ENDPROC(gic_init_secure_percpu)
167 /*************************************************************************
169 * void gic_kick_secondary_cpus(DistributorBase);
171 * void gic_kick_secondary_cpus(void);
173 *************************************************************************/
174 ENTRY(gic_kick_secondary_cpus)
175 #if defined(CONFIG_GICV3)
177 msr ICC_ASGI1R_EL1, x9
179 #elif defined(CONFIG_GICV2)
181 movk w9, #0x100, lsl #16
182 str w9, [x0, GICD_SGIR]
185 ENDPROC(gic_kick_secondary_cpus)
188 /*************************************************************************
190 * void gic_wait_for_interrupt(CpuInterfaceBase);
192 * void gic_wait_for_interrupt(void);
194 * Wait for SGI 0 from master.
196 *************************************************************************/
197 ENTRY(gic_wait_for_interrupt)
198 #if defined(CONFIG_GICV3)
199 gic_wait_for_interrupt_m x9
200 #elif defined(CONFIG_GICV2)
201 gic_wait_for_interrupt_m x0, w9
204 ENDPROC(gic_wait_for_interrupt)