1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
10 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Marius Groeger <mgroeger@sysgo.de>
16 * Copyright 2015 ATS Advanced Telematics Systems GmbH
17 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
24 * ARMv7M does not support ARM instruction mode. However, the
25 * interworking BLX and BX instructions do encode the ARM/Thumb
26 * field in bit 0. This means that when executing any Branch
27 * and eXchange instruction we must set bit 0 to one to guarantee
28 * that we keep the processor in Thumb instruction mode. From The
29 * ARMv7-M Instruction Set A4.1.1:
30 * "ARMv7-M only supports the Thumb instruction execution state,
31 * therefore the value of address bit [0] must be 1 in interworking
32 * instructions, otherwise a fault occurs."
34 unsigned long do_go_exec(ulong (*entry)(int, char * const []),
35 int argc, char *const argv[])
37 ulong addr = (ulong)entry | 1;
40 return entry(argc, argv);