1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 /* for now: just dummy functions to satisfy the linker */
13 #include <asm/cache.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 * Flush range from all levels of d-cache/unified-cache.
19 * Affects the range [start, start + size - 1].
21 __weak void flush_cache(unsigned long start, unsigned long size)
23 flush_dcache_range(start, start + size);
27 * Default implementation:
28 * do a range flush for the entire range
30 __weak void flush_dcache_all(void)
36 * Default implementation of enable_caches()
37 * Real implementation should be in platform code
39 __weak void enable_caches(void)
41 puts("WARNING: Caches not enabled\n");
44 __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
46 /* An empty stub, real implementation should be in platform code */
48 __weak void flush_dcache_range(unsigned long start, unsigned long stop)
50 /* An empty stub, real implementation should be in platform code */
53 int check_cache_range(unsigned long start, unsigned long stop)
57 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
60 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
64 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
71 #ifdef CONFIG_SYS_NONCACHED_MEMORY
73 * Reserve one MMU section worth of address space below the malloc() area that
74 * will be mapped uncached.
76 static unsigned long noncached_start;
77 static unsigned long noncached_end;
78 static unsigned long noncached_next;
80 void noncached_set_region(void)
82 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
83 mmu_set_region_dcache_behaviour(noncached_start,
84 noncached_end - noncached_start,
89 void noncached_init(void)
91 phys_addr_t start, end;
94 /* If this calculation changes, update board_f.c:reserve_noncached() */
95 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
96 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
99 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
101 noncached_start = start;
103 noncached_next = start;
105 noncached_set_region();
108 phys_addr_t noncached_alloc(size_t size, size_t align)
110 phys_addr_t next = ALIGN(noncached_next, align);
112 if (next >= noncached_end || (noncached_end - next) < size)
115 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
116 noncached_next = next + size;
120 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
122 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
123 void invalidate_l2_cache(void)
125 unsigned int val = 0;
127 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
128 : : "r" (val) : "cc");
133 int arch_reserve_mmu(void)
135 return arm_reserve_mmu();
138 __weak int arm_reserve_mmu(void)
140 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
141 /* reserve TLB table */
142 gd->arch.tlb_size = PGTABLE_SIZE;
143 gd->relocaddr -= gd->arch.tlb_size;
145 /* round down to next 64 kB limit */
146 gd->relocaddr &= ~(0x10000 - 1);
148 gd->arch.tlb_addr = gd->relocaddr;
149 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
150 gd->arch.tlb_addr + gd->arch.tlb_size);
152 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
154 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
155 * with location within secure ram.
157 gd->arch.tlb_allocated = gd->arch.tlb_addr;