1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 /* for now: just dummy functions to satisfy the linker */
13 DECLARE_GLOBAL_DATA_PTR;
16 * Flush range from all levels of d-cache/unified-cache.
17 * Affects the range [start, start + size - 1].
19 __weak void flush_cache(unsigned long start, unsigned long size)
21 flush_dcache_range(start, start + size);
25 * Default implementation:
26 * do a range flush for the entire range
28 __weak void flush_dcache_all(void)
34 * Default implementation of enable_caches()
35 * Real implementation should be in platform code
37 __weak void enable_caches(void)
39 puts("WARNING: Caches not enabled\n");
42 __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
44 /* An empty stub, real implementation should be in platform code */
46 __weak void flush_dcache_range(unsigned long start, unsigned long stop)
48 /* An empty stub, real implementation should be in platform code */
51 int check_cache_range(unsigned long start, unsigned long stop)
55 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
58 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
62 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
69 #ifdef CONFIG_SYS_NONCACHED_MEMORY
71 * Reserve one MMU section worth of address space below the malloc() area that
72 * will be mapped uncached.
74 static unsigned long noncached_start;
75 static unsigned long noncached_end;
76 static unsigned long noncached_next;
78 void noncached_init(void)
80 phys_addr_t start, end;
83 /* If this calculation changes, update board_f.c:reserve_noncached() */
84 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
85 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
88 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
90 noncached_start = start;
92 noncached_next = start;
94 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
95 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
99 phys_addr_t noncached_alloc(size_t size, size_t align)
101 phys_addr_t next = ALIGN(noncached_next, align);
103 if (next >= noncached_end || (noncached_end - next) < size)
106 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
107 noncached_next = next + size;
111 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
113 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
114 void invalidate_l2_cache(void)
116 unsigned int val = 0;
118 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
119 : : "r" (val) : "cc");
124 int arch_reserve_mmu(void)
126 return arm_reserve_mmu();
129 __weak int arm_reserve_mmu(void)
131 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
132 /* reserve TLB table */
133 gd->arch.tlb_size = PGTABLE_SIZE;
134 gd->relocaddr -= gd->arch.tlb_size;
136 /* round down to next 64 kB limit */
137 gd->relocaddr &= ~(0x10000 - 1);
139 gd->arch.tlb_addr = gd->relocaddr;
140 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
141 gd->arch.tlb_addr + gd->arch.tlb_size);
143 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
145 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
146 * with location within secure ram.
148 gd->arch.tlb_allocated = gd->arch.tlb_addr;