3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 __weak void arm_init_before_mmu(void)
21 __weak void arm_init_domains(void)
25 static void cp_delay (void)
29 /* copro seems to need some delay between reading and writing */
30 for (i = 0; i < 100; i++)
32 asm volatile("" : : : "memory");
35 void set_section_dcache(int section, enum dcache_option option)
37 #ifdef CONFIG_ARMV7_LPAE
38 u64 *page_table = (u64 *)gd->arch.tlb_addr;
39 /* Need to set the access flag to not fault */
40 u64 value = TTB_SECT_AP | TTB_SECT_AF;
42 u32 *page_table = (u32 *)gd->arch.tlb_addr;
43 u32 value = TTB_SECT_AP;
46 /* Add the page offset */
47 value |= ((u32)section << MMU_SECTION_SHIFT);
49 /* Add caching bits */
53 page_table[section] = value;
56 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
58 debug("%s: Warning: not implemented\n", __func__);
61 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
62 enum dcache_option option)
64 #ifdef CONFIG_ARMV7_LPAE
65 u64 *page_table = (u64 *)gd->arch.tlb_addr;
67 u32 *page_table = (u32 *)gd->arch.tlb_addr;
69 unsigned long upto, end;
71 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
72 start = start >> MMU_SECTION_SHIFT;
73 debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
75 for (upto = start; upto < end; upto++)
76 set_section_dcache(upto, option);
77 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
80 __weak void dram_bank_mmu_setup(int bank)
85 debug("%s: bank: %d\n", __func__, bank);
86 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
87 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
88 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
90 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
91 set_section_dcache(i, DCACHE_WRITETHROUGH);
92 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
93 set_section_dcache(i, DCACHE_WRITEALLOC);
95 set_section_dcache(i, DCACHE_WRITEBACK);
100 /* to activate the MMU we need to set up virtual memory: use 1M areas */
101 static inline void mmu_setup(void)
106 arm_init_before_mmu();
107 /* Set up an identity-mapping for all 4GB, rw for everyone */
108 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
109 set_section_dcache(i, DCACHE_OFF);
111 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
112 dram_bank_mmu_setup(i);
115 #ifdef CONFIG_ARMV7_LPAE
116 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
117 for (i = 0; i < 4; i++) {
118 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
119 u64 tpt = gd->arch.tlb_addr + (4096 * i);
120 page_table[i] = tpt | TTB_PAGETABLE;
124 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
125 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
126 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
127 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
129 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
133 /* Set HCTR to enable LPAE */
134 asm volatile("mcr p15, 4, %0, c2, c0, 2"
135 : : "r" (reg) : "memory");
137 asm volatile("mcrr p15, 4, %0, %1, c2"
139 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
142 asm volatile("mcr p15, 4, %0, c10, c2, 0"
143 : : "r" (MEMORY_ATTRIBUTES) : "memory");
145 /* Set TTBCR to enable LPAE */
146 asm volatile("mcr p15, 0, %0, c2, c0, 2"
147 : : "r" (reg) : "memory");
148 /* Set 64-bit TTBR0 */
149 asm volatile("mcrr p15, 0, %0, %1, c2"
151 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
154 asm volatile("mcr p15, 0, %0, c10, c2, 0"
155 : : "r" (MEMORY_ATTRIBUTES) : "memory");
157 #elif defined(CONFIG_CPU_V7)
159 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
160 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
161 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
162 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
163 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
165 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
167 asm volatile("mcr p15, 0, %0, c2, c0, 0"
168 : : "r" (reg) : "memory");
170 /* Copy the page table address to cp15 */
171 asm volatile("mcr p15, 0, %0, c2, c0, 0"
172 : : "r" (gd->arch.tlb_addr) : "memory");
174 /* Set the access control to all-supervisor */
175 asm volatile("mcr p15, 0, %0, c3, c0, 0"
180 /* and enable the mmu */
181 reg = get_cr(); /* get control reg. */
186 static int mmu_enabled(void)
188 return get_cr() & CR_M;
191 /* cache_bit must be either CR_I or CR_C */
192 static void cache_enable(uint32_t cache_bit)
196 /* The data cache is not active unless the mmu is enabled too */
197 if ((cache_bit == CR_C) && !mmu_enabled())
199 reg = get_cr(); /* get control reg. */
201 set_cr(reg | cache_bit);
204 /* cache_bit must be either CR_I or CR_C */
205 static void cache_disable(uint32_t cache_bit)
212 if (cache_bit == CR_C) {
213 /* if cache isn;t enabled no need to disable */
214 if ((reg & CR_C) != CR_C)
216 /* if disabling data cache, disable mmu too */
221 if (cache_bit == (CR_C | CR_M))
223 set_cr(reg & ~cache_bit);
227 #ifdef CONFIG_SYS_ICACHE_OFF
228 void icache_enable (void)
233 void icache_disable (void)
238 int icache_status (void)
240 return 0; /* always off */
243 void icache_enable(void)
248 void icache_disable(void)
253 int icache_status(void)
255 return (get_cr() & CR_I) != 0;
259 #ifdef CONFIG_SYS_DCACHE_OFF
260 void dcache_enable (void)
265 void dcache_disable (void)
270 int dcache_status (void)
272 return 0; /* always off */
275 void dcache_enable(void)
280 void dcache_disable(void)
285 int dcache_status(void)
287 return (get_cr() & CR_C) != 0;