1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 #include <asm/global_data.h>
11 #include <asm/system.h>
12 #include <asm/cache.h>
13 #include <linux/compiler.h>
14 #include <asm/armv7_mpu.h>
16 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
18 DECLARE_GLOBAL_DATA_PTR;
20 #ifdef CONFIG_SYS_ARM_MMU
21 __weak void arm_init_before_mmu(void)
25 static void set_section_phys(int section, phys_addr_t phys,
26 enum dcache_option option)
28 #ifdef CONFIG_ARMV7_LPAE
29 u64 *page_table = (u64 *)gd->arch.tlb_addr;
30 /* Need to set the access flag to not fault */
31 u64 value = TTB_SECT_AP | TTB_SECT_AF;
33 u32 *page_table = (u32 *)gd->arch.tlb_addr;
34 u32 value = TTB_SECT_AP;
37 /* Add the page offset */
40 /* Add caching bits */
44 page_table[section] = value;
47 void set_section_dcache(int section, enum dcache_option option)
49 set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
52 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
54 debug("%s: Warning: not implemented\n", __func__);
57 void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
58 size_t size, enum dcache_option option)
60 #ifdef CONFIG_ARMV7_LPAE
61 u64 *page_table = (u64 *)gd->arch.tlb_addr;
63 u32 *page_table = (u32 *)gd->arch.tlb_addr;
65 unsigned long startpt, stoppt;
66 unsigned long upto, end;
68 /* div by 2 before start + size to avoid phys_addr_t overflow */
69 end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
70 >> (MMU_SECTION_SHIFT - 1);
71 start = start >> MMU_SECTION_SHIFT;
73 #ifdef CONFIG_ARMV7_LPAE
74 debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
77 debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
80 for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
81 set_section_phys(upto, phys, option);
84 * Make sure range is cache line aligned
85 * Only CPU maintains page tables, hence it is safe to always
86 * flush complete cache lines...
89 startpt = (unsigned long)&page_table[start];
90 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
91 stoppt = (unsigned long)&page_table[end];
92 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
93 mmu_page_table_flush(startpt, stoppt);
96 __weak void dram_bank_mmu_setup(int bank)
98 struct bd_info *bd = gd->bd;
101 /* bd->bi_dram is available only after relocation */
102 if ((gd->flags & GD_FLG_RELOC) == 0)
105 debug("%s: bank: %d\n", __func__, bank);
106 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
107 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
108 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
110 set_section_dcache(i, DCACHE_DEFAULT_OPTION);
113 /* to activate the MMU we need to set up virtual memory: use 1M areas */
114 static inline void mmu_setup(void)
119 arm_init_before_mmu();
120 /* Set up an identity-mapping for all 4GB, rw for everyone */
121 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
122 set_section_dcache(i, DCACHE_OFF);
124 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
125 dram_bank_mmu_setup(i);
128 #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
129 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
130 for (i = 0; i < 4; i++) {
131 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
132 u64 tpt = gd->arch.tlb_addr + (4096 * i);
133 page_table[i] = tpt | TTB_PAGETABLE;
137 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
138 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
139 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
140 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
142 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
146 /* Set HTCR to enable LPAE */
147 asm volatile("mcr p15, 4, %0, c2, c0, 2"
148 : : "r" (reg) : "memory");
150 asm volatile("mcrr p15, 4, %0, %1, c2"
152 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
155 asm volatile("mcr p15, 4, %0, c10, c2, 0"
156 : : "r" (MEMORY_ATTRIBUTES) : "memory");
158 /* Set TTBCR to enable LPAE */
159 asm volatile("mcr p15, 0, %0, c2, c0, 2"
160 : : "r" (reg) : "memory");
161 /* Set 64-bit TTBR0 */
162 asm volatile("mcrr p15, 0, %0, %1, c2"
164 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
167 asm volatile("mcr p15, 0, %0, c10, c2, 0"
168 : : "r" (MEMORY_ATTRIBUTES) : "memory");
170 #elif defined(CONFIG_CPU_V7A)
172 /* Set HTCR to disable LPAE */
173 asm volatile("mcr p15, 4, %0, c2, c0, 2"
174 : : "r" (0) : "memory");
176 /* Set TTBCR to disable LPAE */
177 asm volatile("mcr p15, 0, %0, c2, c0, 2"
178 : : "r" (0) : "memory");
181 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
182 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
183 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
184 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
185 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
187 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
189 asm volatile("mcr p15, 0, %0, c2, c0, 0"
190 : : "r" (reg) : "memory");
192 /* Copy the page table address to cp15 */
193 asm volatile("mcr p15, 0, %0, c2, c0, 0"
194 : : "r" (gd->arch.tlb_addr) : "memory");
197 * initial value of Domain Access Control Register (DACR)
198 * Set the access control to client (1U) for each of the 16 domains
200 asm volatile("mcr p15, 0, %0, c3, c0, 0"
201 : : "r" (0x55555555));
203 /* and enable the mmu */
204 reg = get_cr(); /* get control reg. */
208 static int mmu_enabled(void)
210 return get_cr() & CR_M;
212 #endif /* CONFIG_SYS_ARM_MMU */
214 /* cache_bit must be either CR_I or CR_C */
215 static void cache_enable(uint32_t cache_bit)
219 /* The data cache is not active unless the mmu/mpu is enabled too */
220 #ifdef CONFIG_SYS_ARM_MMU
221 if ((cache_bit == CR_C) && !mmu_enabled())
223 #elif defined(CONFIG_SYS_ARM_MPU)
224 if ((cache_bit == CR_C) && !mpu_enabled()) {
225 printf("Consider enabling MPU before enabling caches\n");
229 reg = get_cr(); /* get control reg. */
230 set_cr(reg | cache_bit);
233 /* cache_bit must be either CR_I or CR_C */
234 static void cache_disable(uint32_t cache_bit)
240 if (cache_bit == CR_C) {
241 /* if cache isn;t enabled no need to disable */
242 if ((reg & CR_C) != CR_C)
244 #ifdef CONFIG_SYS_ARM_MMU
245 /* if disabling data cache, disable mmu too */
251 #ifdef CONFIG_SYS_ARM_MMU
252 if (cache_bit == (CR_C | CR_M))
253 #elif defined(CONFIG_SYS_ARM_MPU)
254 if (cache_bit == CR_C)
257 set_cr(reg & ~cache_bit);
261 #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
262 void icache_enable(void)
267 void icache_disable(void)
272 int icache_status(void)
274 return 0; /* always off */
277 void icache_enable(void)
282 void icache_disable(void)
287 int icache_status(void)
289 return (get_cr() & CR_I) != 0;
293 #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
294 void dcache_enable(void)
299 void dcache_disable(void)
304 int dcache_status(void)
306 return 0; /* always off */
309 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
310 enum dcache_option option)
315 void dcache_enable(void)
320 void dcache_disable(void)
325 int dcache_status(void)
327 return (get_cr() & CR_C) != 0;
330 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
331 enum dcache_option option)
333 mmu_set_region_dcache_behaviour_phys(start, start, size, option);