1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 #include <asm/system.h>
11 #include <asm/cache.h>
12 #include <linux/compiler.h>
13 #include <asm/armv7_mpu.h>
15 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
17 DECLARE_GLOBAL_DATA_PTR;
19 #ifdef CONFIG_SYS_ARM_MMU
20 __weak void arm_init_before_mmu(void)
24 __weak void arm_init_domains(void)
28 static void set_section_phys(int section, phys_addr_t phys,
29 enum dcache_option option)
31 #ifdef CONFIG_ARMV7_LPAE
32 u64 *page_table = (u64 *)gd->arch.tlb_addr;
33 /* Need to set the access flag to not fault */
34 u64 value = TTB_SECT_AP | TTB_SECT_AF;
36 u32 *page_table = (u32 *)gd->arch.tlb_addr;
37 u32 value = TTB_SECT_AP;
40 /* Add the page offset */
43 /* Add caching bits */
47 page_table[section] = value;
50 void set_section_dcache(int section, enum dcache_option option)
52 set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
55 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
57 debug("%s: Warning: not implemented\n", __func__);
60 void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
61 size_t size, enum dcache_option option)
63 #ifdef CONFIG_ARMV7_LPAE
64 u64 *page_table = (u64 *)gd->arch.tlb_addr;
66 u32 *page_table = (u32 *)gd->arch.tlb_addr;
68 unsigned long startpt, stoppt;
69 unsigned long upto, end;
71 /* div by 2 before start + size to avoid phys_addr_t overflow */
72 end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
73 >> (MMU_SECTION_SHIFT - 1);
74 start = start >> MMU_SECTION_SHIFT;
76 #ifdef CONFIG_ARMV7_LPAE
77 debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
80 debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
83 for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
84 set_section_phys(upto, phys, option);
87 * Make sure range is cache line aligned
88 * Only CPU maintains page tables, hence it is safe to always
89 * flush complete cache lines...
92 startpt = (unsigned long)&page_table[start];
93 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
94 stoppt = (unsigned long)&page_table[end];
95 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
96 mmu_page_table_flush(startpt, stoppt);
99 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
100 enum dcache_option option)
102 mmu_set_region_dcache_behaviour_phys(start, start, size, option);
105 __weak void dram_bank_mmu_setup(int bank)
107 struct bd_info *bd = gd->bd;
110 /* bd->bi_dram is available only after relocation */
111 if ((gd->flags & GD_FLG_RELOC) == 0)
114 debug("%s: bank: %d\n", __func__, bank);
115 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
116 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
117 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
119 set_section_dcache(i, DCACHE_DEFAULT_OPTION);
122 /* to activate the MMU we need to set up virtual memory: use 1M areas */
123 static inline void mmu_setup(void)
128 arm_init_before_mmu();
129 /* Set up an identity-mapping for all 4GB, rw for everyone */
130 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
131 set_section_dcache(i, DCACHE_OFF);
133 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
134 dram_bank_mmu_setup(i);
137 #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
138 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
139 for (i = 0; i < 4; i++) {
140 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
141 u64 tpt = gd->arch.tlb_addr + (4096 * i);
142 page_table[i] = tpt | TTB_PAGETABLE;
146 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
147 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
148 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
149 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
151 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
155 /* Set HTCR to enable LPAE */
156 asm volatile("mcr p15, 4, %0, c2, c0, 2"
157 : : "r" (reg) : "memory");
159 asm volatile("mcrr p15, 4, %0, %1, c2"
161 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
164 asm volatile("mcr p15, 4, %0, c10, c2, 0"
165 : : "r" (MEMORY_ATTRIBUTES) : "memory");
167 /* Set TTBCR to enable LPAE */
168 asm volatile("mcr p15, 0, %0, c2, c0, 2"
169 : : "r" (reg) : "memory");
170 /* Set 64-bit TTBR0 */
171 asm volatile("mcrr p15, 0, %0, %1, c2"
173 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
176 asm volatile("mcr p15, 0, %0, c10, c2, 0"
177 : : "r" (MEMORY_ATTRIBUTES) : "memory");
179 #elif defined(CONFIG_CPU_V7A)
181 /* Set HTCR to disable LPAE */
182 asm volatile("mcr p15, 4, %0, c2, c0, 2"
183 : : "r" (0) : "memory");
185 /* Set TTBCR to disable LPAE */
186 asm volatile("mcr p15, 0, %0, c2, c0, 2"
187 : : "r" (0) : "memory");
190 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
191 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
192 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
193 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
194 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
196 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
198 asm volatile("mcr p15, 0, %0, c2, c0, 0"
199 : : "r" (reg) : "memory");
201 /* Copy the page table address to cp15 */
202 asm volatile("mcr p15, 0, %0, c2, c0, 0"
203 : : "r" (gd->arch.tlb_addr) : "memory");
205 /* Set the access control to all-supervisor */
206 asm volatile("mcr p15, 0, %0, c3, c0, 0"
211 /* and enable the mmu */
212 reg = get_cr(); /* get control reg. */
216 static int mmu_enabled(void)
218 return get_cr() & CR_M;
220 #endif /* CONFIG_SYS_ARM_MMU */
222 /* cache_bit must be either CR_I or CR_C */
223 static void cache_enable(uint32_t cache_bit)
227 /* The data cache is not active unless the mmu/mpu is enabled too */
228 #ifdef CONFIG_SYS_ARM_MMU
229 if ((cache_bit == CR_C) && !mmu_enabled())
231 #elif defined(CONFIG_SYS_ARM_MPU)
232 if ((cache_bit == CR_C) && !mpu_enabled()) {
233 printf("Consider enabling MPU before enabling caches\n");
237 reg = get_cr(); /* get control reg. */
238 set_cr(reg | cache_bit);
241 /* cache_bit must be either CR_I or CR_C */
242 static void cache_disable(uint32_t cache_bit)
248 if (cache_bit == CR_C) {
249 /* if cache isn;t enabled no need to disable */
250 if ((reg & CR_C) != CR_C)
252 #ifdef CONFIG_SYS_ARM_MMU
253 /* if disabling data cache, disable mmu too */
259 #ifdef CONFIG_SYS_ARM_MMU
260 if (cache_bit == (CR_C | CR_M))
261 #elif defined(CONFIG_SYS_ARM_MPU)
262 if (cache_bit == CR_C)
265 set_cr(reg & ~cache_bit);
269 #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
270 void icache_enable(void)
275 void icache_disable(void)
280 int icache_status(void)
282 return 0; /* always off */
285 void icache_enable(void)
290 void icache_disable(void)
295 int icache_status(void)
297 return (get_cr() & CR_I) != 0;
301 #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
302 void dcache_enable(void)
307 void dcache_disable(void)
312 int dcache_status(void)
314 return 0; /* always off */
317 void dcache_enable(void)
322 void dcache_disable(void)
327 int dcache_status(void)
329 return (get_cr() & CR_C) != 0;