4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/bitmap.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/perf_event.h>
20 #include <linux/platform_device.h>
21 #include <linux/spinlock.h>
22 #include <linux/uaccess.h>
24 #include <asm/cputype.h>
26 #include <asm/irq_regs.h>
28 #include <asm/stacktrace.h>
31 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
32 * another platform that supports more, we need to increase this to be the
33 * largest of all platforms.
35 * ARMv7 supports up to 32 events:
36 * cycle counter CCNT + 31 events counters CNT0..30.
37 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
39 #define ARMPMU_MAX_HWEVENTS 32
41 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
42 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
43 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
45 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
47 /* Set at runtime when we know what CPU type we are. */
48 static struct arm_pmu *cpu_pmu;
51 armpmu_get_pmu_id(void)
60 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
63 armpmu_get_max_events(void)
68 max_events = cpu_pmu->num_events;
72 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
74 int perf_num_counters(void)
76 return armpmu_get_max_events();
78 EXPORT_SYMBOL_GPL(perf_num_counters);
80 #define HW_OP_UNSUPPORTED 0xFFFF
83 PERF_COUNT_HW_CACHE_##_x
85 #define CACHE_OP_UNSUPPORTED 0xFFFF
88 armpmu_map_cache_event(const unsigned (*cache_map)
89 [PERF_COUNT_HW_CACHE_MAX]
90 [PERF_COUNT_HW_CACHE_OP_MAX]
91 [PERF_COUNT_HW_CACHE_RESULT_MAX],
94 unsigned int cache_type, cache_op, cache_result, ret;
96 cache_type = (config >> 0) & 0xff;
97 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
100 cache_op = (config >> 8) & 0xff;
101 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
104 cache_result = (config >> 16) & 0xff;
105 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
108 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
110 if (ret == CACHE_OP_UNSUPPORTED)
117 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
119 int mapping = (*event_map)[config];
120 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
124 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
126 return (int)(config & raw_event_mask);
129 static int map_cpu_event(struct perf_event *event,
130 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
131 const unsigned (*cache_map)
132 [PERF_COUNT_HW_CACHE_MAX]
133 [PERF_COUNT_HW_CACHE_OP_MAX]
134 [PERF_COUNT_HW_CACHE_RESULT_MAX],
137 u64 config = event->attr.config;
139 switch (event->attr.type) {
140 case PERF_TYPE_HARDWARE:
141 return armpmu_map_event(event_map, config);
142 case PERF_TYPE_HW_CACHE:
143 return armpmu_map_cache_event(cache_map, config);
145 return armpmu_map_raw_event(raw_event_mask, config);
152 armpmu_event_set_period(struct perf_event *event,
153 struct hw_perf_event *hwc,
156 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
157 s64 left = local64_read(&hwc->period_left);
158 s64 period = hwc->sample_period;
161 if (unlikely(left <= -period)) {
163 local64_set(&hwc->period_left, left);
164 hwc->last_period = period;
168 if (unlikely(left <= 0)) {
170 local64_set(&hwc->period_left, left);
171 hwc->last_period = period;
175 if (left > (s64)armpmu->max_period)
176 left = armpmu->max_period;
178 local64_set(&hwc->prev_count, (u64)-left);
180 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
182 perf_event_update_userpage(event);
188 armpmu_event_update(struct perf_event *event,
189 struct hw_perf_event *hwc,
190 int idx, int overflow)
192 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
193 u64 delta, prev_raw_count, new_raw_count;
196 prev_raw_count = local64_read(&hwc->prev_count);
197 new_raw_count = armpmu->read_counter(idx);
199 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
200 new_raw_count) != prev_raw_count)
203 new_raw_count &= armpmu->max_period;
204 prev_raw_count &= armpmu->max_period;
207 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
209 delta = new_raw_count - prev_raw_count;
211 local64_add(delta, &event->count);
212 local64_sub(delta, &hwc->period_left);
214 return new_raw_count;
218 armpmu_read(struct perf_event *event)
220 struct hw_perf_event *hwc = &event->hw;
222 /* Don't read disabled counters! */
226 armpmu_event_update(event, hwc, hwc->idx, 0);
230 armpmu_stop(struct perf_event *event, int flags)
232 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
233 struct hw_perf_event *hwc = &event->hw;
236 * ARM pmu always has to update the counter, so ignore
237 * PERF_EF_UPDATE, see comments in armpmu_start().
239 if (!(hwc->state & PERF_HES_STOPPED)) {
240 armpmu->disable(hwc, hwc->idx);
241 barrier(); /* why? */
242 armpmu_event_update(event, hwc, hwc->idx, 0);
243 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
248 armpmu_start(struct perf_event *event, int flags)
250 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
251 struct hw_perf_event *hwc = &event->hw;
254 * ARM pmu always has to reprogram the period, so ignore
255 * PERF_EF_RELOAD, see the comment below.
257 if (flags & PERF_EF_RELOAD)
258 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
262 * Set the period again. Some counters can't be stopped, so when we
263 * were stopped we simply disabled the IRQ source and the counter
264 * may have been left counting. If we don't do this step then we may
265 * get an interrupt too soon or *way* too late if the overflow has
266 * happened since disabling.
268 armpmu_event_set_period(event, hwc, hwc->idx);
269 armpmu->enable(hwc, hwc->idx);
273 armpmu_del(struct perf_event *event, int flags)
275 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
276 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
277 struct hw_perf_event *hwc = &event->hw;
282 armpmu_stop(event, PERF_EF_UPDATE);
283 hw_events->events[idx] = NULL;
284 clear_bit(idx, hw_events->used_mask);
286 perf_event_update_userpage(event);
290 armpmu_add(struct perf_event *event, int flags)
292 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
293 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
294 struct hw_perf_event *hwc = &event->hw;
298 perf_pmu_disable(event->pmu);
300 /* If we don't have a space for the counter then finish early. */
301 idx = armpmu->get_event_idx(hw_events, hwc);
308 * If there is an event in the counter we are going to use then make
309 * sure it is disabled.
312 armpmu->disable(hwc, idx);
313 hw_events->events[idx] = event;
315 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
316 if (flags & PERF_EF_START)
317 armpmu_start(event, PERF_EF_RELOAD);
319 /* Propagate our changes to the userspace mapping. */
320 perf_event_update_userpage(event);
323 perf_pmu_enable(event->pmu);
328 validate_event(struct pmu_hw_events *hw_events,
329 struct perf_event *event)
331 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
332 struct hw_perf_event fake_event = event->hw;
333 struct pmu *leader_pmu = event->group_leader->pmu;
335 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
338 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
342 validate_group(struct perf_event *event)
344 struct perf_event *sibling, *leader = event->group_leader;
345 struct pmu_hw_events fake_pmu;
346 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
349 * Initialise the fake PMU. We only need to populate the
350 * used_mask for the purposes of validation.
352 memset(fake_used_mask, 0, sizeof(fake_used_mask));
353 fake_pmu.used_mask = fake_used_mask;
355 if (!validate_event(&fake_pmu, leader))
358 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
359 if (!validate_event(&fake_pmu, sibling))
363 if (!validate_event(&fake_pmu, event))
369 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
371 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
372 struct platform_device *plat_device = armpmu->plat_device;
373 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
375 return plat->handle_irq(irq, dev, armpmu->handle_irq);
379 armpmu_release_hardware(struct arm_pmu *armpmu)
382 struct platform_device *pmu_device = armpmu->plat_device;
384 irqs = min(pmu_device->num_resources, num_possible_cpus());
386 for (i = 0; i < irqs; ++i) {
387 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
389 irq = platform_get_irq(pmu_device, i);
391 free_irq(irq, armpmu);
394 release_pmu(armpmu->type);
398 armpmu_reserve_hardware(struct arm_pmu *armpmu)
400 struct arm_pmu_platdata *plat;
401 irq_handler_t handle_irq;
402 int i, err, irq, irqs;
403 struct platform_device *pmu_device = armpmu->plat_device;
405 err = reserve_pmu(armpmu->type);
407 pr_warning("unable to reserve pmu\n");
411 plat = dev_get_platdata(&pmu_device->dev);
412 if (plat && plat->handle_irq)
413 handle_irq = armpmu_platform_irq;
415 handle_irq = armpmu->handle_irq;
417 irqs = min(pmu_device->num_resources, num_possible_cpus());
419 pr_err("no irqs for PMUs defined\n");
423 for (i = 0; i < irqs; ++i) {
425 irq = platform_get_irq(pmu_device, i);
430 * If we have a single PMU interrupt that we can't shift,
431 * assume that we're running on a uniprocessor machine and
432 * continue. Otherwise, continue without this interrupt.
434 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
435 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
440 err = request_irq(irq, handle_irq,
441 IRQF_DISABLED | IRQF_NOBALANCING,
444 pr_err("unable to request IRQ%d for ARM PMU counters\n",
446 armpmu_release_hardware(armpmu);
450 cpumask_set_cpu(i, &armpmu->active_irqs);
457 hw_perf_event_destroy(struct perf_event *event)
459 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
460 atomic_t *active_events = &armpmu->active_events;
461 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
463 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
464 armpmu_release_hardware(armpmu);
465 mutex_unlock(pmu_reserve_mutex);
470 event_requires_mode_exclusion(struct perf_event_attr *attr)
472 return attr->exclude_idle || attr->exclude_user ||
473 attr->exclude_kernel || attr->exclude_hv;
477 __hw_perf_event_init(struct perf_event *event)
479 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
480 struct hw_perf_event *hwc = &event->hw;
483 mapping = armpmu->map_event(event);
486 pr_debug("event %x:%llx not supported\n", event->attr.type,
492 * We don't assign an index until we actually place the event onto
493 * hardware. Use -1 to signify that we haven't decided where to put it
494 * yet. For SMP systems, each core has it's own PMU so we can't do any
495 * clever allocation or constraints checking at this point.
498 hwc->config_base = 0;
503 * Check whether we need to exclude the counter from certain modes.
505 if ((!armpmu->set_event_filter ||
506 armpmu->set_event_filter(hwc, &event->attr)) &&
507 event_requires_mode_exclusion(&event->attr)) {
508 pr_debug("ARM performance counters do not support "
514 * Store the event encoding into the config_base field.
516 hwc->config_base |= (unsigned long)mapping;
518 if (!hwc->sample_period) {
519 hwc->sample_period = armpmu->max_period;
520 hwc->last_period = hwc->sample_period;
521 local64_set(&hwc->period_left, hwc->sample_period);
525 if (event->group_leader != event) {
526 err = validate_group(event);
534 static int armpmu_event_init(struct perf_event *event)
536 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
538 atomic_t *active_events = &armpmu->active_events;
540 if (armpmu->map_event(event) == -ENOENT)
543 event->destroy = hw_perf_event_destroy;
545 if (!atomic_inc_not_zero(active_events)) {
546 mutex_lock(&armpmu->reserve_mutex);
547 if (atomic_read(active_events) == 0)
548 err = armpmu_reserve_hardware(armpmu);
551 atomic_inc(active_events);
552 mutex_unlock(&armpmu->reserve_mutex);
558 err = __hw_perf_event_init(event);
560 hw_perf_event_destroy(event);
565 static void armpmu_enable(struct pmu *pmu)
567 struct arm_pmu *armpmu = to_arm_pmu(pmu);
568 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
569 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
575 static void armpmu_disable(struct pmu *pmu)
577 struct arm_pmu *armpmu = to_arm_pmu(pmu);
581 static void __init armpmu_init(struct arm_pmu *armpmu)
583 atomic_set(&armpmu->active_events, 0);
584 mutex_init(&armpmu->reserve_mutex);
586 armpmu->pmu = (struct pmu) {
587 .pmu_enable = armpmu_enable,
588 .pmu_disable = armpmu_disable,
589 .event_init = armpmu_event_init,
592 .start = armpmu_start,
598 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
601 return perf_pmu_register(&armpmu->pmu, name, type);
604 /* Include the PMU-specific implementations. */
605 #include "perf_event_xscale.c"
606 #include "perf_event_v6.c"
607 #include "perf_event_v7.c"
610 * Ensure the PMU has sane values out of reset.
611 * This requires SMP to be available, so exists as a separate initcall.
616 if (cpu_pmu && cpu_pmu->reset)
617 return on_each_cpu(cpu_pmu->reset, NULL, 1);
620 arch_initcall(cpu_pmu_reset);
623 * PMU platform driver and devicetree bindings.
625 static struct of_device_id armpmu_of_device_ids[] = {
626 {.compatible = "arm,cortex-a9-pmu"},
627 {.compatible = "arm,cortex-a8-pmu"},
628 {.compatible = "arm,arm1136-pmu"},
629 {.compatible = "arm,arm1176-pmu"},
633 static struct platform_device_id armpmu_plat_device_ids[] = {
638 static int __devinit armpmu_device_probe(struct platform_device *pdev)
640 cpu_pmu->plat_device = pdev;
644 static struct platform_driver armpmu_driver = {
647 .of_match_table = armpmu_of_device_ids,
649 .probe = armpmu_device_probe,
650 .id_table = armpmu_plat_device_ids,
653 static int __init register_pmu_driver(void)
655 return platform_driver_register(&armpmu_driver);
657 device_initcall(register_pmu_driver);
659 static struct pmu_hw_events *armpmu_get_cpu_events(void)
661 return &__get_cpu_var(cpu_hw_events);
664 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
667 for_each_possible_cpu(cpu) {
668 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
669 events->events = per_cpu(hw_events, cpu);
670 events->used_mask = per_cpu(used_mask, cpu);
671 raw_spin_lock_init(&events->pmu_lock);
673 armpmu->get_hw_events = armpmu_get_cpu_events;
674 armpmu->type = ARM_PMU_DEVICE_CPU;
678 * CPU PMU identification and registration.
681 init_hw_perf_events(void)
683 unsigned long cpuid = read_cpuid_id();
684 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
685 unsigned long part_number = (cpuid & 0xFFF0);
688 if (0x41 == implementor) {
689 switch (part_number) {
690 case 0xB360: /* ARM1136 */
691 case 0xB560: /* ARM1156 */
692 case 0xB760: /* ARM1176 */
693 cpu_pmu = armv6pmu_init();
695 case 0xB020: /* ARM11mpcore */
696 cpu_pmu = armv6mpcore_pmu_init();
698 case 0xC080: /* Cortex-A8 */
699 cpu_pmu = armv7_a8_pmu_init();
701 case 0xC090: /* Cortex-A9 */
702 cpu_pmu = armv7_a9_pmu_init();
704 case 0xC050: /* Cortex-A5 */
705 cpu_pmu = armv7_a5_pmu_init();
707 case 0xC0F0: /* Cortex-A15 */
708 cpu_pmu = armv7_a15_pmu_init();
711 /* Intel CPUs [xscale]. */
712 } else if (0x69 == implementor) {
713 part_number = (cpuid >> 13) & 0x7;
714 switch (part_number) {
716 cpu_pmu = xscale1pmu_init();
719 cpu_pmu = xscale2pmu_init();
725 pr_info("enabled with %s PMU driver, %d counters available\n",
726 cpu_pmu->name, cpu_pmu->num_events);
727 cpu_pmu_init(cpu_pmu);
728 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
730 pr_info("no hardware support available\n");
735 early_initcall(init_hw_perf_events);
738 * Callchain handling code.
742 * The registers we're interested in are at the end of the variable
743 * length saved register structure. The fp points at the end of this
744 * structure so the address of this struct is:
745 * (struct frame_tail *)(xxx->fp)-1
747 * This code has been adapted from the ARM OProfile support.
750 struct frame_tail __user *fp;
753 } __attribute__((packed));
756 * Get the return address for a single stackframe and return a pointer to the
759 static struct frame_tail __user *
760 user_backtrace(struct frame_tail __user *tail,
761 struct perf_callchain_entry *entry)
763 struct frame_tail buftail;
765 /* Also check accessibility of one struct frame_tail beyond */
766 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
768 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
771 perf_callchain_store(entry, buftail.lr);
774 * Frame pointers should strictly progress back up the stack
775 * (towards higher addresses).
777 if (tail + 1 >= buftail.fp)
780 return buftail.fp - 1;
784 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
786 struct frame_tail __user *tail;
789 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
791 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
792 tail && !((unsigned long)tail & 0x3))
793 tail = user_backtrace(tail, entry);
797 * Gets called by walk_stackframe() for every stackframe. This will be called
798 * whist unwinding the stackframe and is like a subroutine return so we use
802 callchain_trace(struct stackframe *fr,
805 struct perf_callchain_entry *entry = data;
806 perf_callchain_store(entry, fr->pc);
811 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
813 struct stackframe fr;
815 fr.fp = regs->ARM_fp;
816 fr.sp = regs->ARM_sp;
817 fr.lr = regs->ARM_lr;
818 fr.pc = regs->ARM_pc;
819 walk_stackframe(&fr, callchain_trace, entry);