4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/perf_event.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/uaccess.h>
23 #include <asm/cputype.h>
25 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
30 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
31 * another platform that supports more, we need to increase this to be the
32 * largest of all platforms.
34 * ARMv7 supports up to 32 events:
35 * cycle counter CCNT + 31 events counters CNT0..30.
36 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
38 #define ARMPMU_MAX_HWEVENTS 32
40 /* The events for a given CPU. */
41 struct cpu_hw_events {
43 * The events that are active on the CPU for the given index.
45 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
48 * A 1 bit for an index indicates that the counter is being used for
49 * an event. A 0 means that the counter can be used.
51 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
54 * Hardware lock to serialize accesses to PMU registers. Needed for the
55 * read/modify/write sequences.
57 raw_spinlock_t pmu_lock;
59 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
63 enum arm_perf_pmu_ids id;
64 enum arm_pmu_type type;
65 cpumask_t active_irqs;
67 irqreturn_t (*handle_irq)(int irq_num, void *dev);
68 void (*enable)(struct hw_perf_event *evt, int idx);
69 void (*disable)(struct hw_perf_event *evt, int idx);
70 int (*get_event_idx)(struct cpu_hw_events *cpuc,
71 struct hw_perf_event *hwc);
72 int (*set_event_filter)(struct hw_perf_event *evt,
73 struct perf_event_attr *attr);
74 u32 (*read_counter)(int idx);
75 void (*write_counter)(int idx, u32 val);
78 void (*reset)(void *);
79 int (*map_event)(struct perf_event *event);
81 atomic_t active_events;
82 struct mutex reserve_mutex;
84 struct platform_device *plat_device;
85 struct cpu_hw_events *(*get_hw_events)(void);
88 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
90 /* Set at runtime when we know what CPU type we are. */
91 static struct arm_pmu *armpmu;
94 armpmu_get_pmu_id(void)
103 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
106 armpmu_get_max_events(void)
111 max_events = armpmu->num_events;
115 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
117 int perf_num_counters(void)
119 return armpmu_get_max_events();
121 EXPORT_SYMBOL_GPL(perf_num_counters);
123 #define HW_OP_UNSUPPORTED 0xFFFF
126 PERF_COUNT_HW_CACHE_##_x
128 #define CACHE_OP_UNSUPPORTED 0xFFFF
131 armpmu_map_cache_event(const unsigned (*cache_map)
132 [PERF_COUNT_HW_CACHE_MAX]
133 [PERF_COUNT_HW_CACHE_OP_MAX]
134 [PERF_COUNT_HW_CACHE_RESULT_MAX],
137 unsigned int cache_type, cache_op, cache_result, ret;
139 cache_type = (config >> 0) & 0xff;
140 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
143 cache_op = (config >> 8) & 0xff;
144 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
147 cache_result = (config >> 16) & 0xff;
148 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
151 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
153 if (ret == CACHE_OP_UNSUPPORTED)
160 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
162 int mapping = (*event_map)[config];
163 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
167 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
169 return (int)(config & raw_event_mask);
172 static int map_cpu_event(struct perf_event *event,
173 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
174 const unsigned (*cache_map)
175 [PERF_COUNT_HW_CACHE_MAX]
176 [PERF_COUNT_HW_CACHE_OP_MAX]
177 [PERF_COUNT_HW_CACHE_RESULT_MAX],
180 u64 config = event->attr.config;
182 switch (event->attr.type) {
183 case PERF_TYPE_HARDWARE:
184 return armpmu_map_event(event_map, config);
185 case PERF_TYPE_HW_CACHE:
186 return armpmu_map_cache_event(cache_map, config);
188 return armpmu_map_raw_event(raw_event_mask, config);
195 armpmu_event_set_period(struct perf_event *event,
196 struct hw_perf_event *hwc,
199 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
200 s64 left = local64_read(&hwc->period_left);
201 s64 period = hwc->sample_period;
204 if (unlikely(left <= -period)) {
206 local64_set(&hwc->period_left, left);
207 hwc->last_period = period;
211 if (unlikely(left <= 0)) {
213 local64_set(&hwc->period_left, left);
214 hwc->last_period = period;
218 if (left > (s64)armpmu->max_period)
219 left = armpmu->max_period;
221 local64_set(&hwc->prev_count, (u64)-left);
223 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
225 perf_event_update_userpage(event);
231 armpmu_event_update(struct perf_event *event,
232 struct hw_perf_event *hwc,
233 int idx, int overflow)
235 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
236 u64 delta, prev_raw_count, new_raw_count;
239 prev_raw_count = local64_read(&hwc->prev_count);
240 new_raw_count = armpmu->read_counter(idx);
242 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
243 new_raw_count) != prev_raw_count)
246 new_raw_count &= armpmu->max_period;
247 prev_raw_count &= armpmu->max_period;
250 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
252 delta = new_raw_count - prev_raw_count;
254 local64_add(delta, &event->count);
255 local64_sub(delta, &hwc->period_left);
257 return new_raw_count;
261 armpmu_read(struct perf_event *event)
263 struct hw_perf_event *hwc = &event->hw;
265 /* Don't read disabled counters! */
269 armpmu_event_update(event, hwc, hwc->idx, 0);
273 armpmu_stop(struct perf_event *event, int flags)
275 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
276 struct hw_perf_event *hwc = &event->hw;
279 * ARM pmu always has to update the counter, so ignore
280 * PERF_EF_UPDATE, see comments in armpmu_start().
282 if (!(hwc->state & PERF_HES_STOPPED)) {
283 armpmu->disable(hwc, hwc->idx);
284 barrier(); /* why? */
285 armpmu_event_update(event, hwc, hwc->idx, 0);
286 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
291 armpmu_start(struct perf_event *event, int flags)
293 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
294 struct hw_perf_event *hwc = &event->hw;
297 * ARM pmu always has to reprogram the period, so ignore
298 * PERF_EF_RELOAD, see the comment below.
300 if (flags & PERF_EF_RELOAD)
301 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
305 * Set the period again. Some counters can't be stopped, so when we
306 * were stopped we simply disabled the IRQ source and the counter
307 * may have been left counting. If we don't do this step then we may
308 * get an interrupt too soon or *way* too late if the overflow has
309 * happened since disabling.
311 armpmu_event_set_period(event, hwc, hwc->idx);
312 armpmu->enable(hwc, hwc->idx);
316 armpmu_del(struct perf_event *event, int flags)
318 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
319 struct cpu_hw_events *cpuc = armpmu->get_hw_events();
320 struct hw_perf_event *hwc = &event->hw;
325 armpmu_stop(event, PERF_EF_UPDATE);
326 cpuc->events[idx] = NULL;
327 clear_bit(idx, cpuc->used_mask);
329 perf_event_update_userpage(event);
333 armpmu_add(struct perf_event *event, int flags)
335 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
336 struct cpu_hw_events *cpuc = armpmu->get_hw_events();
337 struct hw_perf_event *hwc = &event->hw;
341 perf_pmu_disable(event->pmu);
343 /* If we don't have a space for the counter then finish early. */
344 idx = armpmu->get_event_idx(cpuc, hwc);
351 * If there is an event in the counter we are going to use then make
352 * sure it is disabled.
355 armpmu->disable(hwc, idx);
356 cpuc->events[idx] = event;
358 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
359 if (flags & PERF_EF_START)
360 armpmu_start(event, PERF_EF_RELOAD);
362 /* Propagate our changes to the userspace mapping. */
363 perf_event_update_userpage(event);
366 perf_pmu_enable(event->pmu);
371 validate_event(struct cpu_hw_events *cpuc,
372 struct perf_event *event)
374 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
375 struct hw_perf_event fake_event = event->hw;
376 struct pmu *leader_pmu = event->group_leader->pmu;
378 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
381 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
385 validate_group(struct perf_event *event)
387 struct perf_event *sibling, *leader = event->group_leader;
388 struct cpu_hw_events fake_pmu;
390 memset(&fake_pmu, 0, sizeof(fake_pmu));
392 if (!validate_event(&fake_pmu, leader))
395 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
396 if (!validate_event(&fake_pmu, sibling))
400 if (!validate_event(&fake_pmu, event))
406 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
408 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
409 struct platform_device *plat_device = armpmu->plat_device;
410 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
412 return plat->handle_irq(irq, dev, armpmu->handle_irq);
416 armpmu_release_hardware(struct arm_pmu *armpmu)
419 struct platform_device *pmu_device = armpmu->plat_device;
421 irqs = min(pmu_device->num_resources, num_possible_cpus());
423 for (i = 0; i < irqs; ++i) {
424 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
426 irq = platform_get_irq(pmu_device, i);
428 free_irq(irq, armpmu);
431 release_pmu(armpmu->type);
435 armpmu_reserve_hardware(struct arm_pmu *armpmu)
437 struct arm_pmu_platdata *plat;
438 irq_handler_t handle_irq;
439 int i, err, irq, irqs;
440 struct platform_device *pmu_device = armpmu->plat_device;
442 err = reserve_pmu(armpmu->type);
444 pr_warning("unable to reserve pmu\n");
448 plat = dev_get_platdata(&pmu_device->dev);
449 if (plat && plat->handle_irq)
450 handle_irq = armpmu_platform_irq;
452 handle_irq = armpmu->handle_irq;
454 irqs = min(pmu_device->num_resources, num_possible_cpus());
456 pr_err("no irqs for PMUs defined\n");
460 for (i = 0; i < irqs; ++i) {
462 irq = platform_get_irq(pmu_device, i);
467 * If we have a single PMU interrupt that we can't shift,
468 * assume that we're running on a uniprocessor machine and
469 * continue. Otherwise, continue without this interrupt.
471 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
472 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
477 err = request_irq(irq, handle_irq,
478 IRQF_DISABLED | IRQF_NOBALANCING,
481 pr_err("unable to request IRQ%d for ARM PMU counters\n",
483 armpmu_release_hardware(armpmu);
487 cpumask_set_cpu(i, &armpmu->active_irqs);
494 hw_perf_event_destroy(struct perf_event *event)
496 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
497 atomic_t *active_events = &armpmu->active_events;
498 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
500 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
501 armpmu_release_hardware(armpmu);
502 mutex_unlock(pmu_reserve_mutex);
507 event_requires_mode_exclusion(struct perf_event_attr *attr)
509 return attr->exclude_idle || attr->exclude_user ||
510 attr->exclude_kernel || attr->exclude_hv;
514 __hw_perf_event_init(struct perf_event *event)
516 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
517 struct hw_perf_event *hwc = &event->hw;
520 mapping = armpmu->map_event(event);
523 pr_debug("event %x:%llx not supported\n", event->attr.type,
529 * We don't assign an index until we actually place the event onto
530 * hardware. Use -1 to signify that we haven't decided where to put it
531 * yet. For SMP systems, each core has it's own PMU so we can't do any
532 * clever allocation or constraints checking at this point.
535 hwc->config_base = 0;
540 * Check whether we need to exclude the counter from certain modes.
542 if ((!armpmu->set_event_filter ||
543 armpmu->set_event_filter(hwc, &event->attr)) &&
544 event_requires_mode_exclusion(&event->attr)) {
545 pr_debug("ARM performance counters do not support "
551 * Store the event encoding into the config_base field.
553 hwc->config_base |= (unsigned long)mapping;
555 if (!hwc->sample_period) {
556 hwc->sample_period = armpmu->max_period;
557 hwc->last_period = hwc->sample_period;
558 local64_set(&hwc->period_left, hwc->sample_period);
562 if (event->group_leader != event) {
563 err = validate_group(event);
571 static int armpmu_event_init(struct perf_event *event)
573 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
575 atomic_t *active_events = &armpmu->active_events;
577 if (armpmu->map_event(event) == -ENOENT)
580 event->destroy = hw_perf_event_destroy;
582 if (!atomic_inc_not_zero(active_events)) {
583 mutex_lock(&armpmu->reserve_mutex);
584 if (atomic_read(active_events) == 0)
585 err = armpmu_reserve_hardware(armpmu);
588 atomic_inc(active_events);
589 mutex_unlock(&armpmu->reserve_mutex);
595 err = __hw_perf_event_init(event);
597 hw_perf_event_destroy(event);
602 static void armpmu_enable(struct pmu *pmu)
604 struct arm_pmu *armpmu = to_arm_pmu(pmu);
605 /* Enable all of the perf events on hardware. */
606 int idx, enabled = 0;
607 struct cpu_hw_events *cpuc = armpmu->get_hw_events();
609 for (idx = 0; idx < armpmu->num_events; ++idx) {
610 struct perf_event *event = cpuc->events[idx];
615 armpmu->enable(&event->hw, idx);
623 static void armpmu_disable(struct pmu *pmu)
625 struct arm_pmu *armpmu = to_arm_pmu(pmu);
629 static void __init armpmu_init(struct arm_pmu *armpmu)
631 atomic_set(&armpmu->active_events, 0);
632 mutex_init(&armpmu->reserve_mutex);
634 armpmu->pmu = (struct pmu) {
635 .pmu_enable = armpmu_enable,
636 .pmu_disable = armpmu_disable,
637 .event_init = armpmu_event_init,
640 .start = armpmu_start,
646 static int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
649 return perf_pmu_register(&armpmu->pmu, name, type);
652 /* Include the PMU-specific implementations. */
653 #include "perf_event_xscale.c"
654 #include "perf_event_v6.c"
655 #include "perf_event_v7.c"
658 * Ensure the PMU has sane values out of reset.
659 * This requires SMP to be available, so exists as a separate initcall.
664 if (armpmu && armpmu->reset)
665 return on_each_cpu(armpmu->reset, NULL, 1);
668 arch_initcall(armpmu_reset);
671 * PMU platform driver and devicetree bindings.
673 static struct of_device_id armpmu_of_device_ids[] = {
674 {.compatible = "arm,cortex-a9-pmu"},
675 {.compatible = "arm,cortex-a8-pmu"},
676 {.compatible = "arm,arm1136-pmu"},
677 {.compatible = "arm,arm1176-pmu"},
681 static struct platform_device_id armpmu_plat_device_ids[] = {
686 static int __devinit armpmu_device_probe(struct platform_device *pdev)
688 armpmu->plat_device = pdev;
692 static struct platform_driver armpmu_driver = {
695 .of_match_table = armpmu_of_device_ids,
697 .probe = armpmu_device_probe,
698 .id_table = armpmu_plat_device_ids,
701 static int __init register_pmu_driver(void)
703 return platform_driver_register(&armpmu_driver);
705 device_initcall(register_pmu_driver);
707 static struct cpu_hw_events *armpmu_get_cpu_events(void)
709 return &__get_cpu_var(cpu_hw_events);
712 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
715 for_each_possible_cpu(cpu) {
716 struct cpu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
717 raw_spin_lock_init(&events->pmu_lock);
719 armpmu->get_hw_events = armpmu_get_cpu_events;
720 armpmu->type = ARM_PMU_DEVICE_CPU;
724 * CPU PMU identification and registration.
727 init_hw_perf_events(void)
729 unsigned long cpuid = read_cpuid_id();
730 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
731 unsigned long part_number = (cpuid & 0xFFF0);
734 if (0x41 == implementor) {
735 switch (part_number) {
736 case 0xB360: /* ARM1136 */
737 case 0xB560: /* ARM1156 */
738 case 0xB760: /* ARM1176 */
739 armpmu = armv6pmu_init();
741 case 0xB020: /* ARM11mpcore */
742 armpmu = armv6mpcore_pmu_init();
744 case 0xC080: /* Cortex-A8 */
745 armpmu = armv7_a8_pmu_init();
747 case 0xC090: /* Cortex-A9 */
748 armpmu = armv7_a9_pmu_init();
750 case 0xC050: /* Cortex-A5 */
751 armpmu = armv7_a5_pmu_init();
753 case 0xC0F0: /* Cortex-A15 */
754 armpmu = armv7_a15_pmu_init();
757 /* Intel CPUs [xscale]. */
758 } else if (0x69 == implementor) {
759 part_number = (cpuid >> 13) & 0x7;
760 switch (part_number) {
762 armpmu = xscale1pmu_init();
765 armpmu = xscale2pmu_init();
771 pr_info("enabled with %s PMU driver, %d counters available\n",
772 armpmu->name, armpmu->num_events);
773 cpu_pmu_init(armpmu);
774 armpmu_register(armpmu, "cpu", PERF_TYPE_RAW);
776 pr_info("no hardware support available\n");
781 early_initcall(init_hw_perf_events);
784 * Callchain handling code.
788 * The registers we're interested in are at the end of the variable
789 * length saved register structure. The fp points at the end of this
790 * structure so the address of this struct is:
791 * (struct frame_tail *)(xxx->fp)-1
793 * This code has been adapted from the ARM OProfile support.
796 struct frame_tail __user *fp;
799 } __attribute__((packed));
802 * Get the return address for a single stackframe and return a pointer to the
805 static struct frame_tail __user *
806 user_backtrace(struct frame_tail __user *tail,
807 struct perf_callchain_entry *entry)
809 struct frame_tail buftail;
811 /* Also check accessibility of one struct frame_tail beyond */
812 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
814 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
817 perf_callchain_store(entry, buftail.lr);
820 * Frame pointers should strictly progress back up the stack
821 * (towards higher addresses).
823 if (tail + 1 >= buftail.fp)
826 return buftail.fp - 1;
830 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
832 struct frame_tail __user *tail;
835 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
837 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
838 tail && !((unsigned long)tail & 0x3))
839 tail = user_backtrace(tail, entry);
843 * Gets called by walk_stackframe() for every stackframe. This will be called
844 * whist unwinding the stackframe and is like a subroutine return so we use
848 callchain_trace(struct stackframe *fr,
851 struct perf_callchain_entry *entry = data;
852 perf_callchain_store(entry, fr->pc);
857 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
859 struct stackframe fr;
861 fr.fp = regs->ARM_fp;
862 fr.sp = regs->ARM_sp;
863 fr.lr = regs->ARM_lr;
864 fr.pc = regs->ARM_pc;
865 walk_stackframe(&fr, callchain_trace, entry);