4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/bitmap.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/perf_event.h>
20 #include <linux/platform_device.h>
21 #include <linux/spinlock.h>
22 #include <linux/uaccess.h>
23 #include <linux/pm_runtime.h>
25 #include <asm/cputype.h>
27 #include <asm/irq_regs.h>
29 #include <asm/stacktrace.h>
32 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
33 * another platform that supports more, we need to increase this to be the
34 * largest of all platforms.
36 * ARMv7 supports up to 32 events:
37 * cycle counter CCNT + 31 events counters CNT0..30.
38 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
40 #define ARMPMU_MAX_HWEVENTS 32
42 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
43 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
44 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
46 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
48 /* Set at runtime when we know what CPU type we are. */
49 static struct arm_pmu *cpu_pmu;
51 const char *perf_pmu_name(void)
56 return cpu_pmu->pmu.name;
58 EXPORT_SYMBOL_GPL(perf_pmu_name);
60 int perf_num_counters(void)
65 max_events = cpu_pmu->num_events;
69 EXPORT_SYMBOL_GPL(perf_num_counters);
71 #define HW_OP_UNSUPPORTED 0xFFFF
74 PERF_COUNT_HW_CACHE_##_x
76 #define CACHE_OP_UNSUPPORTED 0xFFFF
79 armpmu_map_cache_event(const unsigned (*cache_map)
80 [PERF_COUNT_HW_CACHE_MAX]
81 [PERF_COUNT_HW_CACHE_OP_MAX]
82 [PERF_COUNT_HW_CACHE_RESULT_MAX],
85 unsigned int cache_type, cache_op, cache_result, ret;
87 cache_type = (config >> 0) & 0xff;
88 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
91 cache_op = (config >> 8) & 0xff;
92 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
95 cache_result = (config >> 16) & 0xff;
96 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
99 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
101 if (ret == CACHE_OP_UNSUPPORTED)
108 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
110 int mapping = (*event_map)[config];
111 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
115 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
117 return (int)(config & raw_event_mask);
120 static int map_cpu_event(struct perf_event *event,
121 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
122 const unsigned (*cache_map)
123 [PERF_COUNT_HW_CACHE_MAX]
124 [PERF_COUNT_HW_CACHE_OP_MAX]
125 [PERF_COUNT_HW_CACHE_RESULT_MAX],
128 u64 config = event->attr.config;
130 switch (event->attr.type) {
131 case PERF_TYPE_HARDWARE:
132 return armpmu_map_event(event_map, config);
133 case PERF_TYPE_HW_CACHE:
134 return armpmu_map_cache_event(cache_map, config);
136 return armpmu_map_raw_event(raw_event_mask, config);
143 armpmu_event_set_period(struct perf_event *event,
144 struct hw_perf_event *hwc,
147 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
148 s64 left = local64_read(&hwc->period_left);
149 s64 period = hwc->sample_period;
152 if (unlikely(left <= -period)) {
154 local64_set(&hwc->period_left, left);
155 hwc->last_period = period;
159 if (unlikely(left <= 0)) {
161 local64_set(&hwc->period_left, left);
162 hwc->last_period = period;
166 if (left > (s64)armpmu->max_period)
167 left = armpmu->max_period;
169 local64_set(&hwc->prev_count, (u64)-left);
171 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
173 perf_event_update_userpage(event);
179 armpmu_event_update(struct perf_event *event,
180 struct hw_perf_event *hwc,
183 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
184 u64 delta, prev_raw_count, new_raw_count;
187 prev_raw_count = local64_read(&hwc->prev_count);
188 new_raw_count = armpmu->read_counter(idx);
190 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
191 new_raw_count) != prev_raw_count)
194 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
196 local64_add(delta, &event->count);
197 local64_sub(delta, &hwc->period_left);
199 return new_raw_count;
203 armpmu_read(struct perf_event *event)
205 struct hw_perf_event *hwc = &event->hw;
207 /* Don't read disabled counters! */
211 armpmu_event_update(event, hwc, hwc->idx);
215 armpmu_stop(struct perf_event *event, int flags)
217 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
218 struct hw_perf_event *hwc = &event->hw;
221 * ARM pmu always has to update the counter, so ignore
222 * PERF_EF_UPDATE, see comments in armpmu_start().
224 if (!(hwc->state & PERF_HES_STOPPED)) {
225 armpmu->disable(hwc, hwc->idx);
226 barrier(); /* why? */
227 armpmu_event_update(event, hwc, hwc->idx);
228 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
233 armpmu_start(struct perf_event *event, int flags)
235 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
236 struct hw_perf_event *hwc = &event->hw;
239 * ARM pmu always has to reprogram the period, so ignore
240 * PERF_EF_RELOAD, see the comment below.
242 if (flags & PERF_EF_RELOAD)
243 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
247 * Set the period again. Some counters can't be stopped, so when we
248 * were stopped we simply disabled the IRQ source and the counter
249 * may have been left counting. If we don't do this step then we may
250 * get an interrupt too soon or *way* too late if the overflow has
251 * happened since disabling.
253 armpmu_event_set_period(event, hwc, hwc->idx);
254 armpmu->enable(hwc, hwc->idx);
258 armpmu_del(struct perf_event *event, int flags)
260 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
261 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
262 struct hw_perf_event *hwc = &event->hw;
267 armpmu_stop(event, PERF_EF_UPDATE);
268 hw_events->events[idx] = NULL;
269 clear_bit(idx, hw_events->used_mask);
271 perf_event_update_userpage(event);
275 armpmu_add(struct perf_event *event, int flags)
277 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
278 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
279 struct hw_perf_event *hwc = &event->hw;
283 perf_pmu_disable(event->pmu);
285 /* If we don't have a space for the counter then finish early. */
286 idx = armpmu->get_event_idx(hw_events, hwc);
293 * If there is an event in the counter we are going to use then make
294 * sure it is disabled.
297 armpmu->disable(hwc, idx);
298 hw_events->events[idx] = event;
300 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
301 if (flags & PERF_EF_START)
302 armpmu_start(event, PERF_EF_RELOAD);
304 /* Propagate our changes to the userspace mapping. */
305 perf_event_update_userpage(event);
308 perf_pmu_enable(event->pmu);
313 validate_event(struct pmu_hw_events *hw_events,
314 struct perf_event *event)
316 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
317 struct hw_perf_event fake_event = event->hw;
318 struct pmu *leader_pmu = event->group_leader->pmu;
320 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
323 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
327 validate_group(struct perf_event *event)
329 struct perf_event *sibling, *leader = event->group_leader;
330 struct pmu_hw_events fake_pmu;
331 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
334 * Initialise the fake PMU. We only need to populate the
335 * used_mask for the purposes of validation.
337 memset(fake_used_mask, 0, sizeof(fake_used_mask));
338 fake_pmu.used_mask = fake_used_mask;
340 if (!validate_event(&fake_pmu, leader))
343 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
344 if (!validate_event(&fake_pmu, sibling))
348 if (!validate_event(&fake_pmu, event))
354 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
356 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
357 struct platform_device *plat_device = armpmu->plat_device;
358 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
360 return plat->handle_irq(irq, dev, armpmu->handle_irq);
364 armpmu_release_hardware(struct arm_pmu *armpmu)
367 struct platform_device *pmu_device = armpmu->plat_device;
369 irqs = min(pmu_device->num_resources, num_possible_cpus());
371 for (i = 0; i < irqs; ++i) {
372 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
374 irq = platform_get_irq(pmu_device, i);
376 free_irq(irq, armpmu);
379 pm_runtime_put_sync(&pmu_device->dev);
380 release_pmu(armpmu->type);
384 armpmu_reserve_hardware(struct arm_pmu *armpmu)
386 struct arm_pmu_platdata *plat;
387 irq_handler_t handle_irq;
388 int i, err, irq, irqs;
389 struct platform_device *pmu_device = armpmu->plat_device;
394 err = reserve_pmu(armpmu->type);
396 pr_warning("unable to reserve pmu\n");
400 plat = dev_get_platdata(&pmu_device->dev);
401 if (plat && plat->handle_irq)
402 handle_irq = armpmu_platform_irq;
404 handle_irq = armpmu->handle_irq;
406 irqs = min(pmu_device->num_resources, num_possible_cpus());
408 pr_err("no irqs for PMUs defined\n");
412 pm_runtime_get_sync(&pmu_device->dev);
414 for (i = 0; i < irqs; ++i) {
416 irq = platform_get_irq(pmu_device, i);
421 * If we have a single PMU interrupt that we can't shift,
422 * assume that we're running on a uniprocessor machine and
423 * continue. Otherwise, continue without this interrupt.
425 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
426 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
431 err = request_irq(irq, handle_irq,
432 IRQF_DISABLED | IRQF_NOBALANCING,
435 pr_err("unable to request IRQ%d for ARM PMU counters\n",
437 armpmu_release_hardware(armpmu);
441 cpumask_set_cpu(i, &armpmu->active_irqs);
448 hw_perf_event_destroy(struct perf_event *event)
450 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
451 atomic_t *active_events = &armpmu->active_events;
452 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
454 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
455 armpmu_release_hardware(armpmu);
456 mutex_unlock(pmu_reserve_mutex);
461 event_requires_mode_exclusion(struct perf_event_attr *attr)
463 return attr->exclude_idle || attr->exclude_user ||
464 attr->exclude_kernel || attr->exclude_hv;
468 __hw_perf_event_init(struct perf_event *event)
470 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
471 struct hw_perf_event *hwc = &event->hw;
474 mapping = armpmu->map_event(event);
477 pr_debug("event %x:%llx not supported\n", event->attr.type,
483 * We don't assign an index until we actually place the event onto
484 * hardware. Use -1 to signify that we haven't decided where to put it
485 * yet. For SMP systems, each core has it's own PMU so we can't do any
486 * clever allocation or constraints checking at this point.
489 hwc->config_base = 0;
494 * Check whether we need to exclude the counter from certain modes.
496 if ((!armpmu->set_event_filter ||
497 armpmu->set_event_filter(hwc, &event->attr)) &&
498 event_requires_mode_exclusion(&event->attr)) {
499 pr_debug("ARM performance counters do not support "
505 * Store the event encoding into the config_base field.
507 hwc->config_base |= (unsigned long)mapping;
509 if (!hwc->sample_period) {
511 * For non-sampling runs, limit the sample_period to half
512 * of the counter width. That way, the new counter value
513 * is far less likely to overtake the previous one unless
514 * you have some serious IRQ latency issues.
516 hwc->sample_period = armpmu->max_period >> 1;
517 hwc->last_period = hwc->sample_period;
518 local64_set(&hwc->period_left, hwc->sample_period);
522 if (event->group_leader != event) {
523 err = validate_group(event);
531 static int armpmu_event_init(struct perf_event *event)
533 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
535 atomic_t *active_events = &armpmu->active_events;
537 /* does not support taken branch sampling */
538 if (has_branch_stack(event))
541 if (armpmu->map_event(event) == -ENOENT)
544 event->destroy = hw_perf_event_destroy;
546 if (!atomic_inc_not_zero(active_events)) {
547 mutex_lock(&armpmu->reserve_mutex);
548 if (atomic_read(active_events) == 0)
549 err = armpmu_reserve_hardware(armpmu);
552 atomic_inc(active_events);
553 mutex_unlock(&armpmu->reserve_mutex);
559 err = __hw_perf_event_init(event);
561 hw_perf_event_destroy(event);
566 static void armpmu_enable(struct pmu *pmu)
568 struct arm_pmu *armpmu = to_arm_pmu(pmu);
569 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
570 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
576 static void armpmu_disable(struct pmu *pmu)
578 struct arm_pmu *armpmu = to_arm_pmu(pmu);
582 #ifdef CONFIG_PM_RUNTIME
583 static int armpmu_runtime_resume(struct device *dev)
585 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
587 if (plat && plat->runtime_resume)
588 return plat->runtime_resume(dev);
593 static int armpmu_runtime_suspend(struct device *dev)
595 struct arm_pmu_platdata *plat = dev_get_platdata(dev);
597 if (plat && plat->runtime_suspend)
598 return plat->runtime_suspend(dev);
604 static void __init armpmu_init(struct arm_pmu *armpmu)
606 atomic_set(&armpmu->active_events, 0);
607 mutex_init(&armpmu->reserve_mutex);
609 armpmu->pmu = (struct pmu) {
610 .pmu_enable = armpmu_enable,
611 .pmu_disable = armpmu_disable,
612 .event_init = armpmu_event_init,
615 .start = armpmu_start,
621 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
624 return perf_pmu_register(&armpmu->pmu, name, type);
627 /* Include the PMU-specific implementations. */
628 #include "perf_event_xscale.c"
629 #include "perf_event_v6.c"
630 #include "perf_event_v7.c"
633 * Ensure the PMU has sane values out of reset.
634 * This requires SMP to be available, so exists as a separate initcall.
639 if (cpu_pmu && cpu_pmu->reset)
640 return on_each_cpu(cpu_pmu->reset, NULL, 1);
643 arch_initcall(cpu_pmu_reset);
646 * PMU platform driver and devicetree bindings.
648 static struct of_device_id armpmu_of_device_ids[] = {
649 {.compatible = "arm,cortex-a15-pmu"},
650 {.compatible = "arm,cortex-a9-pmu"},
651 {.compatible = "arm,cortex-a8-pmu"},
652 {.compatible = "arm,cortex-a7-pmu"},
653 {.compatible = "arm,cortex-a5-pmu"},
654 {.compatible = "arm,arm11mpcore-pmu"},
655 {.compatible = "arm,arm1176-pmu"},
656 {.compatible = "arm,arm1136-pmu"},
660 static struct platform_device_id armpmu_plat_device_ids[] = {
665 static int __devinit armpmu_device_probe(struct platform_device *pdev)
670 cpu_pmu->plat_device = pdev;
674 static const struct dev_pm_ops armpmu_dev_pm_ops = {
675 SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
678 static struct platform_driver armpmu_driver = {
681 .pm = &armpmu_dev_pm_ops,
682 .of_match_table = armpmu_of_device_ids,
684 .probe = armpmu_device_probe,
685 .id_table = armpmu_plat_device_ids,
688 static int __init register_pmu_driver(void)
690 return platform_driver_register(&armpmu_driver);
692 device_initcall(register_pmu_driver);
694 static struct pmu_hw_events *armpmu_get_cpu_events(void)
696 return &__get_cpu_var(cpu_hw_events);
699 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
702 for_each_possible_cpu(cpu) {
703 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
704 events->events = per_cpu(hw_events, cpu);
705 events->used_mask = per_cpu(used_mask, cpu);
706 raw_spin_lock_init(&events->pmu_lock);
708 armpmu->get_hw_events = armpmu_get_cpu_events;
709 armpmu->type = ARM_PMU_DEVICE_CPU;
713 * PMU hardware loses all context when a CPU goes offline.
714 * When a CPU is hotplugged back in, since some hardware registers are
715 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
716 * junk values out of them.
718 static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
719 unsigned long action, void *hcpu)
721 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
724 if (cpu_pmu && cpu_pmu->reset)
725 cpu_pmu->reset(NULL);
730 static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
731 .notifier_call = pmu_cpu_notify,
735 * CPU PMU identification and registration.
738 init_hw_perf_events(void)
740 unsigned long cpuid = read_cpuid_id();
741 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
742 unsigned long part_number = (cpuid & 0xFFF0);
745 if (0x41 == implementor) {
746 switch (part_number) {
747 case 0xB360: /* ARM1136 */
748 case 0xB560: /* ARM1156 */
749 case 0xB760: /* ARM1176 */
750 cpu_pmu = armv6pmu_init();
752 case 0xB020: /* ARM11mpcore */
753 cpu_pmu = armv6mpcore_pmu_init();
755 case 0xC080: /* Cortex-A8 */
756 cpu_pmu = armv7_a8_pmu_init();
758 case 0xC090: /* Cortex-A9 */
759 cpu_pmu = armv7_a9_pmu_init();
761 case 0xC050: /* Cortex-A5 */
762 cpu_pmu = armv7_a5_pmu_init();
764 case 0xC0F0: /* Cortex-A15 */
765 cpu_pmu = armv7_a15_pmu_init();
767 case 0xC070: /* Cortex-A7 */
768 cpu_pmu = armv7_a7_pmu_init();
771 /* Intel CPUs [xscale]. */
772 } else if (0x69 == implementor) {
773 part_number = (cpuid >> 13) & 0x7;
774 switch (part_number) {
776 cpu_pmu = xscale1pmu_init();
779 cpu_pmu = xscale2pmu_init();
785 pr_info("enabled with %s PMU driver, %d counters available\n",
786 cpu_pmu->name, cpu_pmu->num_events);
787 cpu_pmu_init(cpu_pmu);
788 register_cpu_notifier(&pmu_cpu_notifier);
789 armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
791 pr_info("no hardware support available\n");
796 early_initcall(init_hw_perf_events);
799 * Callchain handling code.
803 * The registers we're interested in are at the end of the variable
804 * length saved register structure. The fp points at the end of this
805 * structure so the address of this struct is:
806 * (struct frame_tail *)(xxx->fp)-1
808 * This code has been adapted from the ARM OProfile support.
811 struct frame_tail __user *fp;
814 } __attribute__((packed));
817 * Get the return address for a single stackframe and return a pointer to the
820 static struct frame_tail __user *
821 user_backtrace(struct frame_tail __user *tail,
822 struct perf_callchain_entry *entry)
824 struct frame_tail buftail;
826 /* Also check accessibility of one struct frame_tail beyond */
827 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
829 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
832 perf_callchain_store(entry, buftail.lr);
835 * Frame pointers should strictly progress back up the stack
836 * (towards higher addresses).
838 if (tail + 1 >= buftail.fp)
841 return buftail.fp - 1;
845 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
847 struct frame_tail __user *tail;
850 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
852 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
853 tail && !((unsigned long)tail & 0x3))
854 tail = user_backtrace(tail, entry);
858 * Gets called by walk_stackframe() for every stackframe. This will be called
859 * whist unwinding the stackframe and is like a subroutine return so we use
863 callchain_trace(struct stackframe *fr,
866 struct perf_callchain_entry *entry = data;
867 perf_callchain_store(entry, fr->pc);
872 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
874 struct stackframe fr;
876 fr.fp = regs->ARM_fp;
877 fr.sp = regs->ARM_sp;
878 fr.lr = regs->ARM_lr;
879 fr.pc = regs->ARM_pc;
880 walk_stackframe(&fr, callchain_trace, entry);