2 * arch/arm/kernel/kprobes-thumb.c
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
13 #include <linux/module.h>
14 #include <asm/opcodes.h>
20 * True if current instruction is in an IT block.
22 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
25 * Return the condition code to check for the currently executing instruction.
26 * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
27 * in_it_block returns true.
29 #define current_cond(cpsr) ((cpsr >> 12) & 0xf)
32 * Return the PC value for a probe in thumb code.
33 * This is the address of the probed instruction plus 4.
34 * We subtract one because the address will have bit zero set to indicate
35 * a pointer to thumb code.
37 static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
39 return (unsigned long)p->addr - 1 + 4;
43 t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
45 kprobe_opcode_t insn = p->opcode;
46 unsigned long pc = thumb_probe_pc(p);
47 int rn = (insn >> 16) & 0xf;
50 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn];
51 unsigned long rmv = regs->uregs[rm];
52 unsigned int halfwords;
54 if (insn & 0x10) /* TBH */
55 halfwords = ((u16 *)rnv)[rmv];
57 halfwords = ((u8 *)rnv)[rmv];
59 regs->ARM_pc = pc + 2 * halfwords;
63 t32_simulate_mrs(struct kprobe *p, struct pt_regs *regs)
65 kprobe_opcode_t insn = p->opcode;
66 int rd = (insn >> 8) & 0xf;
67 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
68 regs->uregs[rd] = regs->ARM_cpsr & mask;
72 t32_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
74 kprobe_opcode_t insn = p->opcode;
75 unsigned long pc = thumb_probe_pc(p);
77 long offset = insn & 0x7ff; /* imm11 */
78 offset += (insn & 0x003f0000) >> 5; /* imm6 */
79 offset += (insn & 0x00002000) << 4; /* J1 */
80 offset += (insn & 0x00000800) << 7; /* J2 */
81 offset -= (insn & 0x04000000) >> 7; /* Apply sign bit */
83 regs->ARM_pc = pc + (offset * 2);
86 static enum kprobe_insn __kprobes
87 t32_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
89 int cc = (insn >> 22) & 0xf;
90 asi->insn_check_cc = kprobe_condition_checks[cc];
91 asi->insn_handler = t32_simulate_cond_branch;
92 return INSN_GOOD_NO_SLOT;
96 t32_simulate_branch(struct kprobe *p, struct pt_regs *regs)
98 kprobe_opcode_t insn = p->opcode;
99 unsigned long pc = thumb_probe_pc(p);
101 long offset = insn & 0x7ff; /* imm11 */
102 offset += (insn & 0x03ff0000) >> 5; /* imm10 */
103 offset += (insn & 0x00002000) << 9; /* J1 */
104 offset += (insn & 0x00000800) << 10; /* J2 */
105 if (insn & 0x04000000)
106 offset -= 0x00800000; /* Apply sign bit */
108 offset ^= 0x00600000; /* Invert J1 and J2 */
110 if (insn & (1 << 14)) {
112 regs->ARM_lr = (unsigned long)p->addr + 4;
113 if (!(insn & (1 << 12))) {
114 /* BLX so switch to ARM mode */
115 regs->ARM_cpsr &= ~PSR_T_BIT;
120 regs->ARM_pc = pc + (offset * 2);
123 static void __kprobes
124 t32_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
126 kprobe_opcode_t insn = p->opcode;
127 unsigned long addr = thumb_probe_pc(p) & ~3;
128 int rt = (insn >> 12) & 0xf;
131 long offset = insn & 0xfff;
132 if (insn & 0x00800000)
137 if (insn & 0x00400000) {
139 rtv = *(unsigned long *)addr;
141 bx_write_pc(rtv, regs);
144 } else if (insn & 0x00200000) {
146 if (insn & 0x01000000)
152 if (insn & 0x01000000)
158 regs->uregs[rt] = rtv;
161 static enum kprobe_insn __kprobes
162 t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
164 enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi);
166 /* Fixup modified instruction to have halfwords in correct order...*/
167 insn = __mem_to_opcode_arm(asi->insn[0]);
168 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn >> 16);
169 ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0xffff);
174 static void __kprobes
175 t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
177 kprobe_opcode_t insn = p->opcode;
178 unsigned long pc = thumb_probe_pc(p) & ~3;
179 int rt1 = (insn >> 12) & 0xf;
180 int rt2 = (insn >> 8) & 0xf;
181 int rn = (insn >> 16) & 0xf;
183 register unsigned long rt1v asm("r0") = regs->uregs[rt1];
184 register unsigned long rt2v asm("r1") = regs->uregs[rt2];
185 register unsigned long rnv asm("r2") = (rn == 15) ? pc
188 __asm__ __volatile__ (
190 : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
191 : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn)
192 : "lr", "memory", "cc"
196 regs->uregs[rn] = rnv; /* Writeback base register */
197 regs->uregs[rt1] = rt1v;
198 regs->uregs[rt2] = rt2v;
201 static void __kprobes
202 t32_emulate_ldrstr(struct kprobe *p, struct pt_regs *regs)
204 kprobe_opcode_t insn = p->opcode;
205 int rt = (insn >> 12) & 0xf;
206 int rn = (insn >> 16) & 0xf;
209 register unsigned long rtv asm("r0") = regs->uregs[rt];
210 register unsigned long rnv asm("r2") = regs->uregs[rn];
211 register unsigned long rmv asm("r3") = regs->uregs[rm];
213 __asm__ __volatile__ (
215 : "=r" (rtv), "=r" (rnv)
216 : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn)
217 : "lr", "memory", "cc"
220 regs->uregs[rn] = rnv; /* Writeback base register */
221 if (rt == 15) /* Can't be true for a STR as they aren't allowed */
222 bx_write_pc(rtv, regs);
224 regs->uregs[rt] = rtv;
227 static void __kprobes
228 t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
230 kprobe_opcode_t insn = p->opcode;
231 int rd = (insn >> 8) & 0xf;
232 int rn = (insn >> 16) & 0xf;
235 register unsigned long rdv asm("r1") = regs->uregs[rd];
236 register unsigned long rnv asm("r2") = regs->uregs[rn];
237 register unsigned long rmv asm("r3") = regs->uregs[rm];
238 unsigned long cpsr = regs->ARM_cpsr;
240 __asm__ __volatile__ (
241 "msr cpsr_fs, %[cpsr] \n\t"
243 "mrs %[cpsr], cpsr \n\t"
244 : "=r" (rdv), [cpsr] "=r" (cpsr)
245 : "0" (rdv), "r" (rnv), "r" (rmv),
246 "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
247 : "lr", "memory", "cc"
250 regs->uregs[rd] = rdv;
251 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
254 static void __kprobes
255 t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
257 kprobe_opcode_t insn = p->opcode;
258 unsigned long pc = thumb_probe_pc(p);
259 int rd = (insn >> 8) & 0xf;
261 register unsigned long rdv asm("r1") = regs->uregs[rd];
262 register unsigned long rnv asm("r2") = pc & ~3;
264 __asm__ __volatile__ (
267 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
268 : "lr", "memory", "cc"
271 regs->uregs[rd] = rdv;
274 static void __kprobes
275 t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
277 kprobe_opcode_t insn = p->opcode;
278 int rd = (insn >> 8) & 0xf;
279 int rn = (insn >> 16) & 0xf;
281 register unsigned long rdv asm("r1") = regs->uregs[rd];
282 register unsigned long rnv asm("r2") = regs->uregs[rn];
284 __asm__ __volatile__ (
287 : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
288 : "lr", "memory", "cc"
291 regs->uregs[rd] = rdv;
294 static void __kprobes
295 t32_emulate_rdlo12rdhi8rn16rm0_noflags(struct kprobe *p, struct pt_regs *regs)
297 kprobe_opcode_t insn = p->opcode;
298 int rdlo = (insn >> 12) & 0xf;
299 int rdhi = (insn >> 8) & 0xf;
300 int rn = (insn >> 16) & 0xf;
303 register unsigned long rdlov asm("r0") = regs->uregs[rdlo];
304 register unsigned long rdhiv asm("r1") = regs->uregs[rdhi];
305 register unsigned long rnv asm("r2") = regs->uregs[rn];
306 register unsigned long rmv asm("r3") = regs->uregs[rm];
308 __asm__ __volatile__ (
310 : "=r" (rdlov), "=r" (rdhiv)
311 : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv),
312 [fn] "r" (p->ainsn.insn_fn)
313 : "lr", "memory", "cc"
316 regs->uregs[rdlo] = rdlov;
317 regs->uregs[rdhi] = rdhiv;
320 /* These emulation encodings are functionally equivalent... */
321 #define t32_emulate_rd8rn16rm0ra12_noflags \
322 t32_emulate_rdlo12rdhi8rn16rm0_noflags
324 static const union decode_item t32_table_1110_100x_x0xx[] = {
325 /* Load/store multiple instructions */
327 /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
328 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
330 /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
331 /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
332 DECODE_REJECT (0xffc00000, 0xe8000000),
333 /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
334 /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
335 DECODE_REJECT (0xffc00000, 0xe9800000),
337 /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
338 DECODE_REJECT (0xfe508000, 0xe8008000),
339 /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
340 DECODE_REJECT (0xfe50c000, 0xe810c000),
341 /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
342 DECODE_REJECT (0xfe402000, 0xe8002000),
344 /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
345 /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
346 /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
347 /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
348 DECODE_CUSTOM (0xfe400000, 0xe8000000, t32_decode_ldmstm),
353 static const union decode_item t32_table_1110_100x_x1xx[] = {
354 /* Load/store dual, load/store exclusive, table branch */
356 /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
357 /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
358 DECODE_OR (0xff600000, 0xe8600000),
359 /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
360 /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
361 DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd,
362 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
364 /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
365 /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
366 DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch,
367 REGS(NOSP, 0, 0, 0, NOSPPC)),
369 /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
370 /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
371 /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
372 /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
373 /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
374 /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
375 /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
376 /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
377 /* And unallocated instructions... */
381 static const union decode_item t32_table_1110_101x[] = {
382 /* Data-processing (shifted register) */
384 /* TST 1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */
385 /* TEQ 1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */
386 DECODE_EMULATEX (0xff700f00, 0xea100f00, t32_emulate_rd8rn16rm0_rwflags,
387 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
389 /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
390 DECODE_OR (0xfff00f00, 0xeb100f00),
391 /* CMP 1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */
392 DECODE_EMULATEX (0xfff00f00, 0xebb00f00, t32_emulate_rd8rn16rm0_rwflags,
393 REGS(NOPC, 0, 0, 0, NOSPPC)),
395 /* MOV 1110 1010 010x 1111 xxxx xxxx xxxx xxxx */
396 /* MVN 1110 1010 011x 1111 xxxx xxxx xxxx xxxx */
397 DECODE_EMULATEX (0xffcf0000, 0xea4f0000, t32_emulate_rd8rn16rm0_rwflags,
398 REGS(0, 0, NOSPPC, 0, NOSPPC)),
400 /* ??? 1110 1010 101x xxxx xxxx xxxx xxxx xxxx */
401 /* ??? 1110 1010 111x xxxx xxxx xxxx xxxx xxxx */
402 DECODE_REJECT (0xffa00000, 0xeaa00000),
403 /* ??? 1110 1011 001x xxxx xxxx xxxx xxxx xxxx */
404 DECODE_REJECT (0xffe00000, 0xeb200000),
405 /* ??? 1110 1011 100x xxxx xxxx xxxx xxxx xxxx */
406 DECODE_REJECT (0xffe00000, 0xeb800000),
407 /* ??? 1110 1011 111x xxxx xxxx xxxx xxxx xxxx */
408 DECODE_REJECT (0xffe00000, 0xebe00000),
410 /* ADD/SUB SP, SP, Rm, LSL #0..3 */
411 /* 1110 1011 x0xx 1101 x000 1101 xx00 xxxx */
412 DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, t32_emulate_rd8rn16rm0_rwflags,
413 REGS(SP, 0, SP, 0, NOSPPC)),
415 /* ADD/SUB SP, SP, Rm, shift */
416 /* 1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */
417 DECODE_REJECT (0xff4f0f00, 0xeb0d0d00),
419 /* ADD/SUB Rd, SP, Rm, shift */
420 /* 1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */
421 DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, t32_emulate_rd8rn16rm0_rwflags,
422 REGS(SP, 0, NOPC, 0, NOSPPC)),
424 /* AND 1110 1010 000x xxxx xxxx xxxx xxxx xxxx */
425 /* BIC 1110 1010 001x xxxx xxxx xxxx xxxx xxxx */
426 /* ORR 1110 1010 010x xxxx xxxx xxxx xxxx xxxx */
427 /* ORN 1110 1010 011x xxxx xxxx xxxx xxxx xxxx */
428 /* EOR 1110 1010 100x xxxx xxxx xxxx xxxx xxxx */
429 /* PKH 1110 1010 110x xxxx xxxx xxxx xxxx xxxx */
430 /* ADD 1110 1011 000x xxxx xxxx xxxx xxxx xxxx */
431 /* ADC 1110 1011 010x xxxx xxxx xxxx xxxx xxxx */
432 /* SBC 1110 1011 011x xxxx xxxx xxxx xxxx xxxx */
433 /* SUB 1110 1011 101x xxxx xxxx xxxx xxxx xxxx */
434 /* RSB 1110 1011 110x xxxx xxxx xxxx xxxx xxxx */
435 DECODE_EMULATEX (0xfe000000, 0xea000000, t32_emulate_rd8rn16rm0_rwflags,
436 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
441 static const union decode_item t32_table_1111_0x0x___0[] = {
442 /* Data-processing (modified immediate) */
444 /* TST 1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */
445 /* TEQ 1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */
446 DECODE_EMULATEX (0xfb708f00, 0xf0100f00, t32_emulate_rd8rn16rm0_rwflags,
447 REGS(NOSPPC, 0, 0, 0, 0)),
449 /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
450 DECODE_OR (0xfbf08f00, 0xf1100f00),
451 /* CMP 1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */
452 DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, t32_emulate_rd8rn16rm0_rwflags,
453 REGS(NOPC, 0, 0, 0, 0)),
455 /* MOV 1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */
456 /* MVN 1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */
457 DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, t32_emulate_rd8rn16rm0_rwflags,
458 REGS(0, 0, NOSPPC, 0, 0)),
460 /* ??? 1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */
461 DECODE_REJECT (0xfbe08000, 0xf0a00000),
462 /* ??? 1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */
463 /* ??? 1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */
464 DECODE_REJECT (0xfbc08000, 0xf0c00000),
465 /* ??? 1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */
466 DECODE_REJECT (0xfbe08000, 0xf1200000),
467 /* ??? 1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */
468 DECODE_REJECT (0xfbe08000, 0xf1800000),
469 /* ??? 1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */
470 DECODE_REJECT (0xfbe08000, 0xf1e00000),
472 /* ADD Rd, SP, #imm 1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */
473 /* SUB Rd, SP, #imm 1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */
474 DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, t32_emulate_rd8rn16rm0_rwflags,
475 REGS(SP, 0, NOPC, 0, 0)),
477 /* AND 1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */
478 /* BIC 1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */
479 /* ORR 1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */
480 /* ORN 1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */
481 /* EOR 1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */
482 /* ADD 1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */
483 /* ADC 1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */
484 /* SBC 1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */
485 /* SUB 1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */
486 /* RSB 1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */
487 DECODE_EMULATEX (0xfa008000, 0xf0000000, t32_emulate_rd8rn16rm0_rwflags,
488 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
493 static const union decode_item t32_table_1111_0x1x___0[] = {
494 /* Data-processing (plain binary immediate) */
496 /* ADDW Rd, PC, #imm 1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */
497 DECODE_OR (0xfbff8000, 0xf20f0000),
498 /* SUBW Rd, PC, #imm 1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */
499 DECODE_EMULATEX (0xfbff8000, 0xf2af0000, t32_emulate_rd8pc16_noflags,
500 REGS(PC, 0, NOSPPC, 0, 0)),
502 /* ADDW SP, SP, #imm 1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */
503 DECODE_OR (0xfbff8f00, 0xf20d0d00),
504 /* SUBW SP, SP, #imm 1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */
505 DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, t32_emulate_rd8rn16_noflags,
506 REGS(SP, 0, SP, 0, 0)),
508 /* ADDW 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */
509 DECODE_OR (0xfbf08000, 0xf2000000),
510 /* SUBW 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */
511 DECODE_EMULATEX (0xfbf08000, 0xf2a00000, t32_emulate_rd8rn16_noflags,
512 REGS(NOPCX, 0, NOSPPC, 0, 0)),
514 /* MOVW 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */
515 /* MOVT 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */
516 DECODE_EMULATEX (0xfb708000, 0xf2400000, t32_emulate_rd8rn16_noflags,
517 REGS(0, 0, NOSPPC, 0, 0)),
519 /* SSAT16 1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */
520 /* SSAT 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */
521 /* USAT16 1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */
522 /* USAT 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */
523 DECODE_EMULATEX (0xfb508000, 0xf3000000, t32_emulate_rd8rn16rm0_rwflags,
524 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
526 /* SFBX 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */
527 /* UFBX 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */
528 DECODE_EMULATEX (0xfb708000, 0xf3400000, t32_emulate_rd8rn16_noflags,
529 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
531 /* BFC 1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */
532 DECODE_EMULATEX (0xfbff8000, 0xf36f0000, t32_emulate_rd8rn16_noflags,
533 REGS(0, 0, NOSPPC, 0, 0)),
535 /* BFI 1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */
536 DECODE_EMULATEX (0xfbf08000, 0xf3600000, t32_emulate_rd8rn16_noflags,
537 REGS(NOSPPCX, 0, NOSPPC, 0, 0)),
542 static const union decode_item t32_table_1111_0xxx___1[] = {
543 /* Branches and miscellaneous control */
545 /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */
546 DECODE_OR (0xfff0d7ff, 0xf3a08001),
547 /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */
548 DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
549 /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */
550 /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */
551 /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */
552 DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
554 /* MRS Rd, CPSR 1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */
555 DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, t32_simulate_mrs,
556 REGS(0, 0, NOSPPC, 0, 0)),
559 * Unsupported instructions
560 * 1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx
562 * MSR 1111 0011 100x xxxx 10x0 xxxx xxxx xxxx
563 * DBG hint 1111 0011 1010 xxxx 10x0 x000 1111 xxxx
564 * Unallocated hints 1111 0011 1010 xxxx 10x0 x000 xxxx xxxx
565 * CPS 1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx
566 * CLREX/DSB/DMB/ISB 1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx
567 * BXJ 1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx
568 * SUBS PC,LR,#<imm8> 1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx
569 * MRS Rd, SPSR 1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx
570 * SMC 1111 0111 1111 xxxx 1000 xxxx xxxx xxxx
571 * UNDEFINED 1111 0111 1111 xxxx 1010 xxxx xxxx xxxx
572 * ??? 1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx
574 DECODE_REJECT (0xfb80d000, 0xf3808000),
576 /* Bcc 1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */
577 DECODE_CUSTOM (0xf800d000, 0xf0008000, t32_decode_cond_branch),
579 /* BLX 1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */
580 DECODE_OR (0xf800d001, 0xf000c000),
581 /* B 1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */
582 /* BL 1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */
583 DECODE_SIMULATE (0xf8009000, 0xf0009000, t32_simulate_branch),
588 static const union decode_item t32_table_1111_100x_x0x1__1111[] = {
591 /* PLD (literal) 1111 1000 x001 1111 1111 xxxx xxxx xxxx */
592 /* PLI (literal) 1111 1001 x001 1111 1111 xxxx xxxx xxxx */
593 DECODE_SIMULATE (0xfe7ff000, 0xf81ff000, kprobe_simulate_nop),
595 /* PLD{W} (immediate) 1111 1000 10x1 xxxx 1111 xxxx xxxx xxxx */
596 DECODE_OR (0xffd0f000, 0xf890f000),
597 /* PLD{W} (immediate) 1111 1000 00x1 xxxx 1111 1100 xxxx xxxx */
598 DECODE_OR (0xffd0ff00, 0xf810fc00),
599 /* PLI (immediate) 1111 1001 1001 xxxx 1111 xxxx xxxx xxxx */
600 DECODE_OR (0xfff0f000, 0xf990f000),
601 /* PLI (immediate) 1111 1001 0001 xxxx 1111 1100 xxxx xxxx */
602 DECODE_SIMULATEX(0xfff0ff00, 0xf910fc00, kprobe_simulate_nop,
603 REGS(NOPCX, 0, 0, 0, 0)),
605 /* PLD{W} (register) 1111 1000 00x1 xxxx 1111 0000 00xx xxxx */
606 DECODE_OR (0xffd0ffc0, 0xf810f000),
607 /* PLI (register) 1111 1001 0001 xxxx 1111 0000 00xx xxxx */
608 DECODE_SIMULATEX(0xfff0ffc0, 0xf910f000, kprobe_simulate_nop,
609 REGS(NOPCX, 0, 0, 0, NOSPPC)),
611 /* Other unallocated instructions... */
615 static const union decode_item t32_table_1111_100x[] = {
616 /* Store/Load single data item */
618 /* ??? 1111 100x x11x xxxx xxxx xxxx xxxx xxxx */
619 DECODE_REJECT (0xfe600000, 0xf8600000),
621 /* ??? 1111 1001 0101 xxxx xxxx xxxx xxxx xxxx */
622 DECODE_REJECT (0xfff00000, 0xf9500000),
624 /* ??? 1111 100x 0xxx xxxx xxxx 10x0 xxxx xxxx */
625 DECODE_REJECT (0xfe800d00, 0xf8000800),
627 /* STRBT 1111 1000 0000 xxxx xxxx 1110 xxxx xxxx */
628 /* STRHT 1111 1000 0010 xxxx xxxx 1110 xxxx xxxx */
629 /* STRT 1111 1000 0100 xxxx xxxx 1110 xxxx xxxx */
630 /* LDRBT 1111 1000 0001 xxxx xxxx 1110 xxxx xxxx */
631 /* LDRSBT 1111 1001 0001 xxxx xxxx 1110 xxxx xxxx */
632 /* LDRHT 1111 1000 0011 xxxx xxxx 1110 xxxx xxxx */
633 /* LDRSHT 1111 1001 0011 xxxx xxxx 1110 xxxx xxxx */
634 /* LDRT 1111 1000 0101 xxxx xxxx 1110 xxxx xxxx */
635 DECODE_REJECT (0xfe800f00, 0xf8000e00),
637 /* STR{,B,H} Rn,[PC...] 1111 1000 xxx0 1111 xxxx xxxx xxxx xxxx */
638 DECODE_REJECT (0xff1f0000, 0xf80f0000),
640 /* STR{,B,H} PC,[Rn...] 1111 1000 xxx0 xxxx 1111 xxxx xxxx xxxx */
641 DECODE_REJECT (0xff10f000, 0xf800f000),
643 /* LDR (literal) 1111 1000 x101 1111 xxxx xxxx xxxx xxxx */
644 DECODE_SIMULATEX(0xff7f0000, 0xf85f0000, t32_simulate_ldr_literal,
645 REGS(PC, ANY, 0, 0, 0)),
647 /* STR (immediate) 1111 1000 0100 xxxx xxxx 1xxx xxxx xxxx */
648 /* LDR (immediate) 1111 1000 0101 xxxx xxxx 1xxx xxxx xxxx */
649 DECODE_OR (0xffe00800, 0xf8400800),
650 /* STR (immediate) 1111 1000 1100 xxxx xxxx xxxx xxxx xxxx */
651 /* LDR (immediate) 1111 1000 1101 xxxx xxxx xxxx xxxx xxxx */
652 DECODE_EMULATEX (0xffe00000, 0xf8c00000, t32_emulate_ldrstr,
653 REGS(NOPCX, ANY, 0, 0, 0)),
655 /* STR (register) 1111 1000 0100 xxxx xxxx 0000 00xx xxxx */
656 /* LDR (register) 1111 1000 0101 xxxx xxxx 0000 00xx xxxx */
657 DECODE_EMULATEX (0xffe00fc0, 0xf8400000, t32_emulate_ldrstr,
658 REGS(NOPCX, ANY, 0, 0, NOSPPC)),
660 /* LDRB (literal) 1111 1000 x001 1111 xxxx xxxx xxxx xxxx */
661 /* LDRSB (literal) 1111 1001 x001 1111 xxxx xxxx xxxx xxxx */
662 /* LDRH (literal) 1111 1000 x011 1111 xxxx xxxx xxxx xxxx */
663 /* LDRSH (literal) 1111 1001 x011 1111 xxxx xxxx xxxx xxxx */
664 DECODE_SIMULATEX(0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
665 REGS(PC, NOSPPCX, 0, 0, 0)),
667 /* STRB (immediate) 1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */
668 /* STRH (immediate) 1111 1000 0010 xxxx xxxx 1xxx xxxx xxxx */
669 /* LDRB (immediate) 1111 1000 0001 xxxx xxxx 1xxx xxxx xxxx */
670 /* LDRSB (immediate) 1111 1001 0001 xxxx xxxx 1xxx xxxx xxxx */
671 /* LDRH (immediate) 1111 1000 0011 xxxx xxxx 1xxx xxxx xxxx */
672 /* LDRSH (immediate) 1111 1001 0011 xxxx xxxx 1xxx xxxx xxxx */
673 DECODE_OR (0xfec00800, 0xf8000800),
674 /* STRB (immediate) 1111 1000 1000 xxxx xxxx xxxx xxxx xxxx */
675 /* STRH (immediate) 1111 1000 1010 xxxx xxxx xxxx xxxx xxxx */
676 /* LDRB (immediate) 1111 1000 1001 xxxx xxxx xxxx xxxx xxxx */
677 /* LDRSB (immediate) 1111 1001 1001 xxxx xxxx xxxx xxxx xxxx */
678 /* LDRH (immediate) 1111 1000 1011 xxxx xxxx xxxx xxxx xxxx */
679 /* LDRSH (immediate) 1111 1001 1011 xxxx xxxx xxxx xxxx xxxx */
680 DECODE_EMULATEX (0xfec00000, 0xf8800000, t32_emulate_ldrstr,
681 REGS(NOPCX, NOSPPCX, 0, 0, 0)),
683 /* STRB (register) 1111 1000 0000 xxxx xxxx 0000 00xx xxxx */
684 /* STRH (register) 1111 1000 0010 xxxx xxxx 0000 00xx xxxx */
685 /* LDRB (register) 1111 1000 0001 xxxx xxxx 0000 00xx xxxx */
686 /* LDRSB (register) 1111 1001 0001 xxxx xxxx 0000 00xx xxxx */
687 /* LDRH (register) 1111 1000 0011 xxxx xxxx 0000 00xx xxxx */
688 /* LDRSH (register) 1111 1001 0011 xxxx xxxx 0000 00xx xxxx */
689 DECODE_EMULATEX (0xfe800fc0, 0xf8000000, t32_emulate_ldrstr,
690 REGS(NOPCX, NOSPPCX, 0, 0, NOSPPC)),
692 /* Other unallocated instructions... */
696 static const union decode_item t32_table_1111_1010___1111[] = {
697 /* Data-processing (register) */
699 /* ??? 1111 1010 011x xxxx 1111 xxxx 1xxx xxxx */
700 DECODE_REJECT (0xffe0f080, 0xfa60f080),
702 /* SXTH 1111 1010 0000 1111 1111 xxxx 1xxx xxxx */
703 /* UXTH 1111 1010 0001 1111 1111 xxxx 1xxx xxxx */
704 /* SXTB16 1111 1010 0010 1111 1111 xxxx 1xxx xxxx */
705 /* UXTB16 1111 1010 0011 1111 1111 xxxx 1xxx xxxx */
706 /* SXTB 1111 1010 0100 1111 1111 xxxx 1xxx xxxx */
707 /* UXTB 1111 1010 0101 1111 1111 xxxx 1xxx xxxx */
708 DECODE_EMULATEX (0xff8ff080, 0xfa0ff080, t32_emulate_rd8rn16rm0_rwflags,
709 REGS(0, 0, NOSPPC, 0, NOSPPC)),
712 /* ??? 1111 1010 1xxx xxxx 1111 xxxx 0x11 xxxx */
713 DECODE_REJECT (0xff80f0b0, 0xfa80f030),
714 /* ??? 1111 1010 1x11 xxxx 1111 xxxx 0xxx xxxx */
715 DECODE_REJECT (0xffb0f080, 0xfab0f000),
717 /* SADD16 1111 1010 1001 xxxx 1111 xxxx 0000 xxxx */
718 /* SASX 1111 1010 1010 xxxx 1111 xxxx 0000 xxxx */
719 /* SSAX 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx */
720 /* SSUB16 1111 1010 1101 xxxx 1111 xxxx 0000 xxxx */
721 /* SADD8 1111 1010 1000 xxxx 1111 xxxx 0000 xxxx */
722 /* SSUB8 1111 1010 1100 xxxx 1111 xxxx 0000 xxxx */
724 /* QADD16 1111 1010 1001 xxxx 1111 xxxx 0001 xxxx */
725 /* QASX 1111 1010 1010 xxxx 1111 xxxx 0001 xxxx */
726 /* QSAX 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx */
727 /* QSUB16 1111 1010 1101 xxxx 1111 xxxx 0001 xxxx */
728 /* QADD8 1111 1010 1000 xxxx 1111 xxxx 0001 xxxx */
729 /* QSUB8 1111 1010 1100 xxxx 1111 xxxx 0001 xxxx */
731 /* SHADD16 1111 1010 1001 xxxx 1111 xxxx 0010 xxxx */
732 /* SHASX 1111 1010 1010 xxxx 1111 xxxx 0010 xxxx */
733 /* SHSAX 1111 1010 1110 xxxx 1111 xxxx 0010 xxxx */
734 /* SHSUB16 1111 1010 1101 xxxx 1111 xxxx 0010 xxxx */
735 /* SHADD8 1111 1010 1000 xxxx 1111 xxxx 0010 xxxx */
736 /* SHSUB8 1111 1010 1100 xxxx 1111 xxxx 0010 xxxx */
738 /* UADD16 1111 1010 1001 xxxx 1111 xxxx 0100 xxxx */
739 /* UASX 1111 1010 1010 xxxx 1111 xxxx 0100 xxxx */
740 /* USAX 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx */
741 /* USUB16 1111 1010 1101 xxxx 1111 xxxx 0100 xxxx */
742 /* UADD8 1111 1010 1000 xxxx 1111 xxxx 0100 xxxx */
743 /* USUB8 1111 1010 1100 xxxx 1111 xxxx 0100 xxxx */
745 /* UQADD16 1111 1010 1001 xxxx 1111 xxxx 0101 xxxx */
746 /* UQASX 1111 1010 1010 xxxx 1111 xxxx 0101 xxxx */
747 /* UQSAX 1111 1010 1110 xxxx 1111 xxxx 0101 xxxx */
748 /* UQSUB16 1111 1010 1101 xxxx 1111 xxxx 0101 xxxx */
749 /* UQADD8 1111 1010 1000 xxxx 1111 xxxx 0101 xxxx */
750 /* UQSUB8 1111 1010 1100 xxxx 1111 xxxx 0101 xxxx */
752 /* UHADD16 1111 1010 1001 xxxx 1111 xxxx 0110 xxxx */
753 /* UHASX 1111 1010 1010 xxxx 1111 xxxx 0110 xxxx */
754 /* UHSAX 1111 1010 1110 xxxx 1111 xxxx 0110 xxxx */
755 /* UHSUB16 1111 1010 1101 xxxx 1111 xxxx 0110 xxxx */
756 /* UHADD8 1111 1010 1000 xxxx 1111 xxxx 0110 xxxx */
757 /* UHSUB8 1111 1010 1100 xxxx 1111 xxxx 0110 xxxx */
758 DECODE_OR (0xff80f080, 0xfa80f000),
760 /* SXTAH 1111 1010 0000 xxxx 1111 xxxx 1xxx xxxx */
761 /* UXTAH 1111 1010 0001 xxxx 1111 xxxx 1xxx xxxx */
762 /* SXTAB16 1111 1010 0010 xxxx 1111 xxxx 1xxx xxxx */
763 /* UXTAB16 1111 1010 0011 xxxx 1111 xxxx 1xxx xxxx */
764 /* SXTAB 1111 1010 0100 xxxx 1111 xxxx 1xxx xxxx */
765 /* UXTAB 1111 1010 0101 xxxx 1111 xxxx 1xxx xxxx */
766 DECODE_OR (0xff80f080, 0xfa00f080),
768 /* QADD 1111 1010 1000 xxxx 1111 xxxx 1000 xxxx */
769 /* QDADD 1111 1010 1000 xxxx 1111 xxxx 1001 xxxx */
770 /* QSUB 1111 1010 1000 xxxx 1111 xxxx 1010 xxxx */
771 /* QDSUB 1111 1010 1000 xxxx 1111 xxxx 1011 xxxx */
772 DECODE_OR (0xfff0f0c0, 0xfa80f080),
774 /* SEL 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
775 DECODE_OR (0xfff0f0f0, 0xfaa0f080),
777 /* LSL 1111 1010 000x xxxx 1111 xxxx 0000 xxxx */
778 /* LSR 1111 1010 001x xxxx 1111 xxxx 0000 xxxx */
779 /* ASR 1111 1010 010x xxxx 1111 xxxx 0000 xxxx */
780 /* ROR 1111 1010 011x xxxx 1111 xxxx 0000 xxxx */
781 DECODE_EMULATEX (0xff80f0f0, 0xfa00f000, t32_emulate_rd8rn16rm0_rwflags,
782 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
784 /* CLZ 1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
785 DECODE_OR (0xfff0f0f0, 0xfab0f080),
787 /* REV 1111 1010 1001 xxxx 1111 xxxx 1000 xxxx */
788 /* REV16 1111 1010 1001 xxxx 1111 xxxx 1001 xxxx */
789 /* RBIT 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx */
790 /* REVSH 1111 1010 1001 xxxx 1111 xxxx 1011 xxxx */
791 DECODE_EMULATEX (0xfff0f0c0, 0xfa90f080, t32_emulate_rd8rn16_noflags,
792 REGS(NOSPPC, 0, NOSPPC, 0, SAMEAS16)),
794 /* Other unallocated instructions... */
798 static const union decode_item t32_table_1111_1011_0[] = {
799 /* Multiply, multiply accumulate, and absolute difference */
801 /* ??? 1111 1011 0000 xxxx 1111 xxxx 0001 xxxx */
802 DECODE_REJECT (0xfff0f0f0, 0xfb00f010),
803 /* ??? 1111 1011 0111 xxxx 1111 xxxx 0001 xxxx */
804 DECODE_REJECT (0xfff0f0f0, 0xfb70f010),
806 /* SMULxy 1111 1011 0001 xxxx 1111 xxxx 00xx xxxx */
807 DECODE_OR (0xfff0f0c0, 0xfb10f000),
808 /* MUL 1111 1011 0000 xxxx 1111 xxxx 0000 xxxx */
809 /* SMUAD{X} 1111 1011 0010 xxxx 1111 xxxx 000x xxxx */
810 /* SMULWy 1111 1011 0011 xxxx 1111 xxxx 000x xxxx */
811 /* SMUSD{X} 1111 1011 0100 xxxx 1111 xxxx 000x xxxx */
812 /* SMMUL{R} 1111 1011 0101 xxxx 1111 xxxx 000x xxxx */
813 /* USAD8 1111 1011 0111 xxxx 1111 xxxx 0000 xxxx */
814 DECODE_EMULATEX (0xff80f0e0, 0xfb00f000, t32_emulate_rd8rn16rm0_rwflags,
815 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
817 /* ??? 1111 1011 0111 xxxx xxxx xxxx 0001 xxxx */
818 DECODE_REJECT (0xfff000f0, 0xfb700010),
820 /* SMLAxy 1111 1011 0001 xxxx xxxx xxxx 00xx xxxx */
821 DECODE_OR (0xfff000c0, 0xfb100000),
822 /* MLA 1111 1011 0000 xxxx xxxx xxxx 0000 xxxx */
823 /* MLS 1111 1011 0000 xxxx xxxx xxxx 0001 xxxx */
824 /* SMLAD{X} 1111 1011 0010 xxxx xxxx xxxx 000x xxxx */
825 /* SMLAWy 1111 1011 0011 xxxx xxxx xxxx 000x xxxx */
826 /* SMLSD{X} 1111 1011 0100 xxxx xxxx xxxx 000x xxxx */
827 /* SMMLA{R} 1111 1011 0101 xxxx xxxx xxxx 000x xxxx */
828 /* SMMLS{R} 1111 1011 0110 xxxx xxxx xxxx 000x xxxx */
829 /* USADA8 1111 1011 0111 xxxx xxxx xxxx 0000 xxxx */
830 DECODE_EMULATEX (0xff8000c0, 0xfb000000, t32_emulate_rd8rn16rm0ra12_noflags,
831 REGS(NOSPPC, NOSPPCX, NOSPPC, 0, NOSPPC)),
833 /* Other unallocated instructions... */
837 static const union decode_item t32_table_1111_1011_1[] = {
838 /* Long multiply, long multiply accumulate, and divide */
840 /* UMAAL 1111 1011 1110 xxxx xxxx xxxx 0110 xxxx */
841 DECODE_OR (0xfff000f0, 0xfbe00060),
842 /* SMLALxy 1111 1011 1100 xxxx xxxx xxxx 10xx xxxx */
843 DECODE_OR (0xfff000c0, 0xfbc00080),
844 /* SMLALD{X} 1111 1011 1100 xxxx xxxx xxxx 110x xxxx */
845 /* SMLSLD{X} 1111 1011 1101 xxxx xxxx xxxx 110x xxxx */
846 DECODE_OR (0xffe000e0, 0xfbc000c0),
847 /* SMULL 1111 1011 1000 xxxx xxxx xxxx 0000 xxxx */
848 /* UMULL 1111 1011 1010 xxxx xxxx xxxx 0000 xxxx */
849 /* SMLAL 1111 1011 1100 xxxx xxxx xxxx 0000 xxxx */
850 /* UMLAL 1111 1011 1110 xxxx xxxx xxxx 0000 xxxx */
851 DECODE_EMULATEX (0xff9000f0, 0xfb800000, t32_emulate_rdlo12rdhi8rn16rm0_noflags,
852 REGS(NOSPPC, NOSPPC, NOSPPC, 0, NOSPPC)),
854 /* SDIV 1111 1011 1001 xxxx xxxx xxxx 1111 xxxx */
855 /* UDIV 1111 1011 1011 xxxx xxxx xxxx 1111 xxxx */
856 /* Other unallocated instructions... */
860 const union decode_item kprobe_decode_thumb32_table[] = {
863 * Load/store multiple instructions
864 * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
866 DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
869 * Load/store dual, load/store exclusive, table branch
870 * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
872 DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
875 * Data-processing (shifted register)
876 * 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx
878 DECODE_TABLE (0xfe000000, 0xea000000, t32_table_1110_101x),
881 * Coprocessor instructions
882 * 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx
884 DECODE_REJECT (0xfc000000, 0xec000000),
887 * Data-processing (modified immediate)
888 * 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx
890 DECODE_TABLE (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0),
893 * Data-processing (plain binary immediate)
894 * 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx
896 DECODE_TABLE (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0),
899 * Branches and miscellaneous control
900 * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
902 DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
905 * Advanced SIMD element or structure load/store instructions
906 * 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx
908 DECODE_REJECT (0xff100000, 0xf9000000),
912 * 1111 100x x0x1 xxxx 1111 xxxx xxxx xxxx
914 DECODE_TABLE (0xfe50f000, 0xf810f000, t32_table_1111_100x_x0x1__1111),
917 * Store single data item
918 * 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx
919 * Load single data items
920 * 1111 100x xxx1 xxxx xxxx xxxx xxxx xxxx
922 DECODE_TABLE (0xfe000000, 0xf8000000, t32_table_1111_100x),
925 * Data-processing (register)
926 * 1111 1010 xxxx xxxx 1111 xxxx xxxx xxxx
928 DECODE_TABLE (0xff00f000, 0xfa00f000, t32_table_1111_1010___1111),
931 * Multiply, multiply accumulate, and absolute difference
932 * 1111 1011 0xxx xxxx xxxx xxxx xxxx xxxx
934 DECODE_TABLE (0xff800000, 0xfb000000, t32_table_1111_1011_0),
937 * Long multiply, long multiply accumulate, and divide
938 * 1111 1011 1xxx xxxx xxxx xxxx xxxx xxxx
940 DECODE_TABLE (0xff800000, 0xfb800000, t32_table_1111_1011_1),
943 * Coprocessor instructions
944 * 1111 11xx xxxx xxxx xxxx xxxx xxxx xxxx
948 #ifdef CONFIG_ARM_KPROBES_TEST_MODULE
949 EXPORT_SYMBOL_GPL(kprobe_decode_thumb32_table);
952 static void __kprobes
953 t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
955 kprobe_opcode_t insn = p->opcode;
956 unsigned long pc = thumb_probe_pc(p);
957 int rm = (insn >> 3) & 0xf;
958 unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
960 if (insn & (1 << 7)) /* BLX ? */
961 regs->ARM_lr = (unsigned long)p->addr + 2;
963 bx_write_pc(rmv, regs);
966 static void __kprobes
967 t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
969 kprobe_opcode_t insn = p->opcode;
970 unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
971 long index = insn & 0xff;
972 int rt = (insn >> 8) & 0x7;
973 regs->uregs[rt] = base[index];
976 static void __kprobes
977 t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
979 kprobe_opcode_t insn = p->opcode;
980 unsigned long* base = (unsigned long *)regs->ARM_sp;
981 long index = insn & 0xff;
982 int rt = (insn >> 8) & 0x7;
983 if (insn & 0x800) /* LDR */
984 regs->uregs[rt] = base[index];
986 base[index] = regs->uregs[rt];
989 static void __kprobes
990 t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
992 kprobe_opcode_t insn = p->opcode;
993 unsigned long base = (insn & 0x800) ? regs->ARM_sp
994 : (thumb_probe_pc(p) & ~3);
995 long offset = insn & 0xff;
996 int rt = (insn >> 8) & 0x7;
997 regs->uregs[rt] = base + offset * 4;
1000 static void __kprobes
1001 t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
1003 kprobe_opcode_t insn = p->opcode;
1004 long imm = insn & 0x7f;
1005 if (insn & 0x80) /* SUB */
1006 regs->ARM_sp -= imm * 4;
1008 regs->ARM_sp += imm * 4;
1011 static void __kprobes
1012 t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
1014 kprobe_opcode_t insn = p->opcode;
1015 int rn = insn & 0x7;
1016 kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
1017 if (nonzero & 0x800) {
1018 long i = insn & 0x200;
1019 long imm5 = insn & 0xf8;
1020 unsigned long pc = thumb_probe_pc(p);
1021 regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
1025 static void __kprobes
1026 t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
1029 * The 8 IT state bits are split into two parts in CPSR:
1030 * ITSTATE<1:0> are in CPSR<26:25>
1031 * ITSTATE<7:2> are in CPSR<15:10>
1032 * The new IT state is in the lower byte of insn.
1034 kprobe_opcode_t insn = p->opcode;
1035 unsigned long cpsr = regs->ARM_cpsr;
1036 cpsr &= ~PSR_IT_MASK;
1037 cpsr |= (insn & 0xfc) << 8;
1038 cpsr |= (insn & 0x03) << 25;
1039 regs->ARM_cpsr = cpsr;
1042 static void __kprobes
1043 t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
1046 t16_simulate_it(p, regs);
1049 static enum kprobe_insn __kprobes
1050 t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1052 asi->insn_singlestep = t16_singlestep_it;
1053 return INSN_GOOD_NO_SLOT;
1056 static void __kprobes
1057 t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
1059 kprobe_opcode_t insn = p->opcode;
1060 unsigned long pc = thumb_probe_pc(p);
1061 long offset = insn & 0x7f;
1062 offset -= insn & 0x80; /* Apply sign bit */
1063 regs->ARM_pc = pc + (offset * 2);
1066 static enum kprobe_insn __kprobes
1067 t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1069 int cc = (insn >> 8) & 0xf;
1070 asi->insn_check_cc = kprobe_condition_checks[cc];
1071 asi->insn_handler = t16_simulate_cond_branch;
1072 return INSN_GOOD_NO_SLOT;
1075 static void __kprobes
1076 t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
1078 kprobe_opcode_t insn = p->opcode;
1079 unsigned long pc = thumb_probe_pc(p);
1080 long offset = insn & 0x3ff;
1081 offset -= insn & 0x400; /* Apply sign bit */
1082 regs->ARM_pc = pc + (offset * 2);
1085 static unsigned long __kprobes
1086 t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
1088 unsigned long oldcpsr = regs->ARM_cpsr;
1089 unsigned long newcpsr;
1091 __asm__ __volatile__ (
1092 "msr cpsr_fs, %[oldcpsr] \n\t"
1093 "ldmia %[regs], {r0-r7} \n\t"
1095 "stmia %[regs], {r0-r7} \n\t"
1096 "mrs %[newcpsr], cpsr \n\t"
1097 : [newcpsr] "=r" (newcpsr)
1098 : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
1099 [fn] "r" (p->ainsn.insn_fn)
1100 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1101 "lr", "memory", "cc"
1104 return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
1107 static void __kprobes
1108 t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
1110 regs->ARM_cpsr = t16_emulate_loregs(p, regs);
1113 static void __kprobes
1114 t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
1116 unsigned long cpsr = t16_emulate_loregs(p, regs);
1117 if (!in_it_block(cpsr))
1118 regs->ARM_cpsr = cpsr;
1121 static void __kprobes
1122 t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
1124 kprobe_opcode_t insn = p->opcode;
1125 unsigned long pc = thumb_probe_pc(p);
1126 int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
1127 int rm = (insn >> 3) & 0xf;
1129 register unsigned long rdnv asm("r1");
1130 register unsigned long rmv asm("r0");
1131 unsigned long cpsr = regs->ARM_cpsr;
1133 rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
1134 rmv = (rm == 15) ? pc : regs->uregs[rm];
1136 __asm__ __volatile__ (
1137 "msr cpsr_fs, %[cpsr] \n\t"
1139 "mrs %[cpsr], cpsr \n\t"
1140 : "=r" (rdnv), [cpsr] "=r" (cpsr)
1141 : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
1142 : "lr", "memory", "cc"
1148 regs->uregs[rdn] = rdnv;
1149 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
1152 static enum kprobe_insn __kprobes
1153 t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1156 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
1157 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn);
1158 asi->insn_handler = t16_emulate_hiregs;
1162 static void __kprobes
1163 t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
1165 __asm__ __volatile__ (
1166 "ldr r9, [%[regs], #13*4] \n\t"
1167 "ldr r8, [%[regs], #14*4] \n\t"
1168 "ldmia %[regs], {r0-r7} \n\t"
1170 "str r9, [%[regs], #13*4] \n\t"
1172 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1173 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
1174 "lr", "memory", "cc"
1178 static enum kprobe_insn __kprobes
1179 t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1182 * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
1183 * and call it with R9=SP and LR in the register list represented
1186 /* 1st half STMDB R9!,{} */
1187 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe929);
1188 /* 2nd half (register list) */
1189 ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
1190 asi->insn_handler = t16_emulate_push;
1194 static void __kprobes
1195 t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
1197 __asm__ __volatile__ (
1198 "ldr r9, [%[regs], #13*4] \n\t"
1199 "ldmia %[regs], {r0-r7} \n\t"
1201 "stmia %[regs], {r0-r7} \n\t"
1202 "str r9, [%[regs], #13*4] \n\t"
1204 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1205 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
1206 "lr", "memory", "cc"
1210 static void __kprobes
1211 t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
1213 register unsigned long pc asm("r8");
1215 __asm__ __volatile__ (
1216 "ldr r9, [%[regs], #13*4] \n\t"
1217 "ldmia %[regs], {r0-r7} \n\t"
1219 "stmia %[regs], {r0-r7} \n\t"
1220 "str r9, [%[regs], #13*4] \n\t"
1222 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
1223 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
1224 "lr", "memory", "cc"
1227 bx_write_pc(pc, regs);
1230 static enum kprobe_insn __kprobes
1231 t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1234 * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
1235 * and call it with R9=SP and PC in the register list represented
1238 /* 1st half LDMIA R9!,{} */
1239 ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe8b9);
1240 /* 2nd half (register list) */
1241 ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
1242 asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
1243 : t16_emulate_pop_nopc;
1247 static const union decode_item t16_table_1011[] = {
1248 /* Miscellaneous 16-bit instructions */
1250 /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
1251 /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
1252 DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
1254 /* CBZ 1011 00x1 xxxx xxxx */
1255 /* CBNZ 1011 10x1 xxxx xxxx */
1256 DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
1258 /* SXTH 1011 0010 00xx xxxx */
1259 /* SXTB 1011 0010 01xx xxxx */
1260 /* UXTH 1011 0010 10xx xxxx */
1261 /* UXTB 1011 0010 11xx xxxx */
1262 /* REV 1011 1010 00xx xxxx */
1263 /* REV16 1011 1010 01xx xxxx */
1264 /* ??? 1011 1010 10xx xxxx */
1265 /* REVSH 1011 1010 11xx xxxx */
1266 DECODE_REJECT (0xffc0, 0xba80),
1267 DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
1269 /* PUSH 1011 010x xxxx xxxx */
1270 DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push),
1271 /* POP 1011 110x xxxx xxxx */
1272 DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop),
1275 * If-Then, and hints
1276 * 1011 1111 xxxx xxxx
1279 /* YIELD 1011 1111 0001 0000 */
1280 DECODE_OR (0xffff, 0xbf10),
1281 /* SEV 1011 1111 0100 0000 */
1282 DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
1283 /* NOP 1011 1111 0000 0000 */
1284 /* WFE 1011 1111 0010 0000 */
1285 /* WFI 1011 1111 0011 0000 */
1286 DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
1287 /* Unassigned hints 1011 1111 xxxx 0000 */
1288 DECODE_REJECT (0xff0f, 0xbf00),
1289 /* IT 1011 1111 xxxx xxxx */
1290 DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it),
1292 /* SETEND 1011 0110 010x xxxx */
1293 /* CPS 1011 0110 011x xxxx */
1294 /* BKPT 1011 1110 xxxx xxxx */
1295 /* And unallocated instructions... */
1299 const union decode_item kprobe_decode_thumb16_table[] = {
1302 * Shift (immediate), add, subtract, move, and compare
1303 * 00xx xxxx xxxx xxxx
1306 /* CMP (immediate) 0010 1xxx xxxx xxxx */
1307 DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
1309 /* ADD (register) 0001 100x xxxx xxxx */
1310 /* SUB (register) 0001 101x xxxx xxxx */
1311 /* LSL (immediate) 0000 0xxx xxxx xxxx */
1312 /* LSR (immediate) 0000 1xxx xxxx xxxx */
1313 /* ASR (immediate) 0001 0xxx xxxx xxxx */
1314 /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
1315 /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
1316 /* MOV (immediate) 0010 0xxx xxxx xxxx */
1317 /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
1318 /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
1319 DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
1322 * 16-bit Thumb data-processing instructions
1323 * 0100 00xx xxxx xxxx
1326 /* TST (register) 0100 0010 00xx xxxx */
1327 DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
1328 /* CMP (register) 0100 0010 10xx xxxx */
1329 /* CMN (register) 0100 0010 11xx xxxx */
1330 DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
1331 /* AND (register) 0100 0000 00xx xxxx */
1332 /* EOR (register) 0100 0000 01xx xxxx */
1333 /* LSL (register) 0100 0000 10xx xxxx */
1334 /* LSR (register) 0100 0000 11xx xxxx */
1335 /* ASR (register) 0100 0001 00xx xxxx */
1336 /* ADC (register) 0100 0001 01xx xxxx */
1337 /* SBC (register) 0100 0001 10xx xxxx */
1338 /* ROR (register) 0100 0001 11xx xxxx */
1339 /* RSB (immediate) 0100 0010 01xx xxxx */
1340 /* ORR (register) 0100 0011 00xx xxxx */
1341 /* MUL 0100 0011 00xx xxxx */
1342 /* BIC (register) 0100 0011 10xx xxxx */
1343 /* MVN (register) 0100 0011 10xx xxxx */
1344 DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
1347 * Special data instructions and branch and exchange
1348 * 0100 01xx xxxx xxxx
1351 /* BLX pc 0100 0111 1111 1xxx */
1352 DECODE_REJECT (0xfff8, 0x47f8),
1354 /* BX (register) 0100 0111 0xxx xxxx */
1355 /* BLX (register) 0100 0111 1xxx xxxx */
1356 DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
1358 /* ADD pc, pc 0100 0100 1111 1111 */
1359 DECODE_REJECT (0xffff, 0x44ff),
1361 /* ADD (register) 0100 0100 xxxx xxxx */
1362 /* CMP (register) 0100 0101 xxxx xxxx */
1363 /* MOV (register) 0100 0110 xxxx xxxx */
1364 DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
1367 * Load from Literal Pool
1368 * LDR (literal) 0100 1xxx xxxx xxxx
1370 DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
1373 * 16-bit Thumb Load/store instructions
1374 * 0101 xxxx xxxx xxxx
1375 * 011x xxxx xxxx xxxx
1376 * 100x xxxx xxxx xxxx
1379 /* STR (register) 0101 000x xxxx xxxx */
1380 /* STRH (register) 0101 001x xxxx xxxx */
1381 /* STRB (register) 0101 010x xxxx xxxx */
1382 /* LDRSB (register) 0101 011x xxxx xxxx */
1383 /* LDR (register) 0101 100x xxxx xxxx */
1384 /* LDRH (register) 0101 101x xxxx xxxx */
1385 /* LDRB (register) 0101 110x xxxx xxxx */
1386 /* LDRSH (register) 0101 111x xxxx xxxx */
1387 /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
1388 /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
1389 /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
1390 /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
1391 DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
1392 /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
1393 /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
1394 DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
1395 /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
1396 /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
1397 DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
1400 * Generate PC-/SP-relative address
1401 * ADR (literal) 1010 0xxx xxxx xxxx
1402 * ADD (SP plus immediate) 1010 1xxx xxxx xxxx
1404 DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
1407 * Miscellaneous 16-bit instructions
1408 * 1011 xxxx xxxx xxxx
1410 DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
1412 /* STM 1100 0xxx xxxx xxxx */
1413 /* LDM 1100 1xxx xxxx xxxx */
1414 DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
1417 * Conditional branch, and Supervisor Call
1420 /* Permanently UNDEFINED 1101 1110 xxxx xxxx */
1421 /* SVC 1101 1111 xxxx xxxx */
1422 DECODE_REJECT (0xfe00, 0xde00),
1424 /* Conditional branch 1101 xxxx xxxx xxxx */
1425 DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch),
1428 * Unconditional branch
1429 * B 1110 0xxx xxxx xxxx
1431 DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
1435 #ifdef CONFIG_ARM_KPROBES_TEST_MODULE
1436 EXPORT_SYMBOL_GPL(kprobe_decode_thumb16_table);
1439 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
1441 if (unlikely(in_it_block(cpsr)))
1442 return kprobe_condition_checks[current_cond(cpsr)](cpsr);
1446 static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
1449 p->ainsn.insn_handler(p, regs);
1450 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1453 static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
1456 p->ainsn.insn_handler(p, regs);
1457 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
1460 enum kprobe_insn __kprobes
1461 thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1463 asi->insn_singlestep = thumb16_singlestep;
1464 asi->insn_check_cc = thumb_check_cc;
1465 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
1468 enum kprobe_insn __kprobes
1469 thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1471 asi->insn_singlestep = thumb32_singlestep;
1472 asi->insn_check_cc = thumb_check_cc;
1473 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);