2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009, 2010 ARM Limited
17 * Author: Will Deacon <will.deacon@arm.com>
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
24 #define pr_fmt(fmt) "hw-breakpoint: " fmt
26 #include <linux/errno.h>
27 #include <linux/hardirq.h>
28 #include <linux/perf_event.h>
29 #include <linux/hw_breakpoint.h>
30 #include <linux/smp.h>
32 #include <asm/cacheflush.h>
33 #include <asm/cputype.h>
34 #include <asm/current.h>
35 #include <asm/hw_breakpoint.h>
36 #include <asm/kdebug.h>
37 #include <asm/traps.h>
39 /* Breakpoint currently in use for each BRP. */
40 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
42 /* Watchpoint currently in use for each WRP. */
43 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
45 /* Number of BRP/WRP registers on this CPU. */
46 static int core_num_brps;
47 static int core_num_wrps;
49 /* Debug architecture version. */
52 /* Maximum supported watchpoint length. */
53 static u8 max_watchpoint_len;
55 #define READ_WB_REG_CASE(OP2, M, VAL) \
56 case ((OP2 << 4) + M): \
57 ARM_DBG_READ(c ## M, OP2, VAL); \
60 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
61 case ((OP2 << 4) + M): \
62 ARM_DBG_WRITE(c ## M, OP2, VAL);\
65 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
66 READ_WB_REG_CASE(OP2, 0, VAL); \
67 READ_WB_REG_CASE(OP2, 1, VAL); \
68 READ_WB_REG_CASE(OP2, 2, VAL); \
69 READ_WB_REG_CASE(OP2, 3, VAL); \
70 READ_WB_REG_CASE(OP2, 4, VAL); \
71 READ_WB_REG_CASE(OP2, 5, VAL); \
72 READ_WB_REG_CASE(OP2, 6, VAL); \
73 READ_WB_REG_CASE(OP2, 7, VAL); \
74 READ_WB_REG_CASE(OP2, 8, VAL); \
75 READ_WB_REG_CASE(OP2, 9, VAL); \
76 READ_WB_REG_CASE(OP2, 10, VAL); \
77 READ_WB_REG_CASE(OP2, 11, VAL); \
78 READ_WB_REG_CASE(OP2, 12, VAL); \
79 READ_WB_REG_CASE(OP2, 13, VAL); \
80 READ_WB_REG_CASE(OP2, 14, VAL); \
81 READ_WB_REG_CASE(OP2, 15, VAL)
83 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
84 WRITE_WB_REG_CASE(OP2, 0, VAL); \
85 WRITE_WB_REG_CASE(OP2, 1, VAL); \
86 WRITE_WB_REG_CASE(OP2, 2, VAL); \
87 WRITE_WB_REG_CASE(OP2, 3, VAL); \
88 WRITE_WB_REG_CASE(OP2, 4, VAL); \
89 WRITE_WB_REG_CASE(OP2, 5, VAL); \
90 WRITE_WB_REG_CASE(OP2, 6, VAL); \
91 WRITE_WB_REG_CASE(OP2, 7, VAL); \
92 WRITE_WB_REG_CASE(OP2, 8, VAL); \
93 WRITE_WB_REG_CASE(OP2, 9, VAL); \
94 WRITE_WB_REG_CASE(OP2, 10, VAL); \
95 WRITE_WB_REG_CASE(OP2, 11, VAL); \
96 WRITE_WB_REG_CASE(OP2, 12, VAL); \
97 WRITE_WB_REG_CASE(OP2, 13, VAL); \
98 WRITE_WB_REG_CASE(OP2, 14, VAL); \
99 WRITE_WB_REG_CASE(OP2, 15, VAL)
101 static u32 read_wb_reg(int n)
106 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
107 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
108 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
109 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
111 pr_warning("attempt to read from unknown breakpoint "
118 static void write_wb_reg(int n, u32 val)
121 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
122 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
123 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
124 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
126 pr_warning("attempt to write to unknown breakpoint "
132 /* Determine debug architecture. */
133 static u8 get_debug_arch(void)
137 /* Do we implement the extended CPUID interface? */
138 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
139 pr_warn_once("CPUID feature registers not supported. "
140 "Assuming v6 debug is present.\n");
141 return ARM_DEBUG_ARCH_V6;
144 ARM_DBG_READ(c0, 0, didr);
145 return (didr >> 16) & 0xf;
148 u8 arch_get_debug_arch(void)
153 static int debug_arch_supported(void)
155 u8 arch = get_debug_arch();
157 /* We don't support the memory-mapped interface. */
158 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
159 arch >= ARM_DEBUG_ARCH_V7_1;
162 /* Can we determine the watchpoint access type from the fsr? */
163 static int debug_exception_updates_fsr(void)
168 /* Determine number of WRP registers available. */
169 static int get_num_wrp_resources(void)
172 ARM_DBG_READ(c0, 0, didr);
173 return ((didr >> 28) & 0xf) + 1;
176 /* Determine number of BRP registers available. */
177 static int get_num_brp_resources(void)
180 ARM_DBG_READ(c0, 0, didr);
181 return ((didr >> 24) & 0xf) + 1;
184 /* Does this core support mismatch breakpoints? */
185 static int core_has_mismatch_brps(void)
187 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
188 get_num_brp_resources() > 1);
191 /* Determine number of usable WRPs available. */
192 static int get_num_wrps(void)
195 * On debug architectures prior to 7.1, when a watchpoint fires, the
196 * only way to work out which watchpoint it was is by disassembling
197 * the faulting instruction and working out the address of the memory
200 * Furthermore, we can only do this if the watchpoint was precise
201 * since imprecise watchpoints prevent us from calculating register
204 * Providing we have more than 1 breakpoint register, we only report
205 * a single watchpoint register for the time being. This way, we always
206 * know which watchpoint fired. In the future we can either add a
207 * disassembler and address generation emulator, or we can insert a
208 * check to see if the DFAR is set on watchpoint exception entry
209 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
210 * that it is set on some implementations].
212 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
215 return get_num_wrp_resources();
218 /* Determine number of usable BRPs available. */
219 static int get_num_brps(void)
221 int brps = get_num_brp_resources();
222 return core_has_mismatch_brps() ? brps - 1 : brps;
226 * In order to access the breakpoint/watchpoint control registers,
227 * we must be running in debug monitor mode. Unfortunately, we can
228 * be put into halting debug mode at any time by an external debugger
229 * but there is nothing we can do to prevent that.
231 static int monitor_mode_enabled(void)
234 ARM_DBG_READ(c1, 0, dscr);
235 return !!(dscr & ARM_DSCR_MDBGEN);
238 static int enable_monitor_mode(void)
241 ARM_DBG_READ(c1, 0, dscr);
243 /* If monitor mode is already enabled, just return. */
244 if (dscr & ARM_DSCR_MDBGEN)
247 /* Write to the corresponding DSCR. */
248 switch (get_debug_arch()) {
249 case ARM_DEBUG_ARCH_V6:
250 case ARM_DEBUG_ARCH_V6_1:
251 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
253 case ARM_DEBUG_ARCH_V7_ECP14:
254 case ARM_DEBUG_ARCH_V7_1:
255 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
262 /* Check that the write made it through. */
263 ARM_DBG_READ(c1, 0, dscr);
264 if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN),
265 "Failed to enable monitor mode on CPU %d.\n",
273 int hw_breakpoint_slots(int type)
275 if (!debug_arch_supported())
279 * We can be called early, so don't rely on
280 * our static variables being initialised.
284 return get_num_brps();
286 return get_num_wrps();
288 pr_warning("unknown slot type: %d\n", type);
294 * Check if 8-bit byte-address select is available.
295 * This clobbers WRP 0.
297 static u8 get_max_wp_len(void)
300 struct arch_hw_breakpoint_ctrl ctrl;
303 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
306 memset(&ctrl, 0, sizeof(ctrl));
307 ctrl.len = ARM_BREAKPOINT_LEN_8;
308 ctrl_reg = encode_ctrl_reg(ctrl);
310 write_wb_reg(ARM_BASE_WVR, 0);
311 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
312 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
319 u8 arch_get_max_wp_len(void)
321 return max_watchpoint_len;
325 * Install a perf counter breakpoint.
327 int arch_install_hw_breakpoint(struct perf_event *bp)
329 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
330 struct perf_event **slot, **slots;
331 int i, max_slots, ctrl_base, val_base;
334 addr = info->address;
335 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
337 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
339 ctrl_base = ARM_BASE_BCR;
340 val_base = ARM_BASE_BVR;
341 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
342 max_slots = core_num_brps;
345 ctrl_base = ARM_BASE_WCR;
346 val_base = ARM_BASE_WVR;
347 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
348 max_slots = core_num_wrps;
351 for (i = 0; i < max_slots; ++i) {
360 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n"))
363 /* Override the breakpoint data with the step data. */
364 if (info->step_ctrl.enabled) {
365 addr = info->trigger & ~0x3;
366 ctrl = encode_ctrl_reg(info->step_ctrl);
367 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
369 ctrl_base = ARM_BASE_BCR + core_num_brps;
370 val_base = ARM_BASE_BVR + core_num_brps;
374 /* Setup the address register. */
375 write_wb_reg(val_base + i, addr);
377 /* Setup the control register. */
378 write_wb_reg(ctrl_base + i, ctrl);
382 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
384 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
385 struct perf_event **slot, **slots;
386 int i, max_slots, base;
388 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
391 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
392 max_slots = core_num_brps;
396 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
397 max_slots = core_num_wrps;
400 /* Remove the breakpoint. */
401 for (i = 0; i < max_slots; ++i) {
410 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n"))
413 /* Ensure that we disable the mismatch breakpoint. */
414 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
415 info->step_ctrl.enabled) {
417 base = ARM_BASE_BCR + core_num_brps;
420 /* Reset the control register. */
421 write_wb_reg(base + i, 0);
424 static int get_hbp_len(u8 hbp_len)
426 unsigned int len_in_bytes = 0;
429 case ARM_BREAKPOINT_LEN_1:
432 case ARM_BREAKPOINT_LEN_2:
435 case ARM_BREAKPOINT_LEN_4:
438 case ARM_BREAKPOINT_LEN_8:
447 * Check whether bp virtual address is in kernel space.
449 int arch_check_bp_in_kernelspace(struct perf_event *bp)
453 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
456 len = get_hbp_len(info->ctrl.len);
458 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
462 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
463 * Hopefully this will disappear when ptrace can bypass the conversion
464 * to generic breakpoint descriptions.
466 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
467 int *gen_len, int *gen_type)
471 case ARM_BREAKPOINT_EXECUTE:
472 *gen_type = HW_BREAKPOINT_X;
474 case ARM_BREAKPOINT_LOAD:
475 *gen_type = HW_BREAKPOINT_R;
477 case ARM_BREAKPOINT_STORE:
478 *gen_type = HW_BREAKPOINT_W;
480 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
481 *gen_type = HW_BREAKPOINT_RW;
489 case ARM_BREAKPOINT_LEN_1:
490 *gen_len = HW_BREAKPOINT_LEN_1;
492 case ARM_BREAKPOINT_LEN_2:
493 *gen_len = HW_BREAKPOINT_LEN_2;
495 case ARM_BREAKPOINT_LEN_4:
496 *gen_len = HW_BREAKPOINT_LEN_4;
498 case ARM_BREAKPOINT_LEN_8:
499 *gen_len = HW_BREAKPOINT_LEN_8;
509 * Construct an arch_hw_breakpoint from a perf_event.
511 static int arch_build_bp_info(struct perf_event *bp)
513 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
516 switch (bp->attr.bp_type) {
517 case HW_BREAKPOINT_X:
518 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
520 case HW_BREAKPOINT_R:
521 info->ctrl.type = ARM_BREAKPOINT_LOAD;
523 case HW_BREAKPOINT_W:
524 info->ctrl.type = ARM_BREAKPOINT_STORE;
526 case HW_BREAKPOINT_RW:
527 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
534 switch (bp->attr.bp_len) {
535 case HW_BREAKPOINT_LEN_1:
536 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
538 case HW_BREAKPOINT_LEN_2:
539 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
541 case HW_BREAKPOINT_LEN_4:
542 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
544 case HW_BREAKPOINT_LEN_8:
545 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
546 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
547 && max_watchpoint_len >= 8)
554 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
555 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
556 * by the hardware and must be aligned to the appropriate number of
559 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
560 info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
561 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
565 info->address = bp->attr.bp_addr;
568 info->ctrl.privilege = ARM_BREAKPOINT_USER;
569 if (arch_check_bp_in_kernelspace(bp))
570 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
573 info->ctrl.enabled = !bp->attr.disabled;
576 info->ctrl.mismatch = 0;
582 * Validate the arch-specific HW Breakpoint register settings.
584 int arch_validate_hwbkpt_settings(struct perf_event *bp)
586 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
588 u32 offset, alignment_mask = 0x3;
590 /* Ensure that we are in monitor debug mode. */
591 if (!monitor_mode_enabled())
594 /* Build the arch_hw_breakpoint. */
595 ret = arch_build_bp_info(bp);
599 /* Check address alignment. */
600 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
601 alignment_mask = 0x7;
602 offset = info->address & alignment_mask;
609 /* Allow halfword watchpoints and breakpoints. */
610 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
613 /* Allow single byte watchpoint. */
614 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
621 info->address &= ~alignment_mask;
622 info->ctrl.len <<= offset;
624 if (!bp->overflow_handler) {
626 * Mismatch breakpoints are required for single-stepping
629 if (!core_has_mismatch_brps())
632 /* We don't allow mismatch breakpoints in kernel space. */
633 if (arch_check_bp_in_kernelspace(bp))
637 * Per-cpu breakpoints are not supported by our stepping
640 if (!bp->hw.bp_target)
644 * We only support specific access types if the fsr
647 if (!debug_exception_updates_fsr() &&
648 (info->ctrl.type == ARM_BREAKPOINT_LOAD ||
649 info->ctrl.type == ARM_BREAKPOINT_STORE))
658 * Enable/disable single-stepping over the breakpoint bp at address addr.
660 static void enable_single_step(struct perf_event *bp, u32 addr)
662 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
664 arch_uninstall_hw_breakpoint(bp);
665 info->step_ctrl.mismatch = 1;
666 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
667 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
668 info->step_ctrl.privilege = info->ctrl.privilege;
669 info->step_ctrl.enabled = 1;
670 info->trigger = addr;
671 arch_install_hw_breakpoint(bp);
674 static void disable_single_step(struct perf_event *bp)
676 arch_uninstall_hw_breakpoint(bp);
677 counter_arch_bp(bp)->step_ctrl.enabled = 0;
678 arch_install_hw_breakpoint(bp);
681 static void watchpoint_handler(unsigned long addr, unsigned int fsr,
682 struct pt_regs *regs)
685 u32 val, ctrl_reg, alignment_mask;
686 struct perf_event *wp, **slots;
687 struct arch_hw_breakpoint *info;
688 struct arch_hw_breakpoint_ctrl ctrl;
690 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
692 for (i = 0; i < core_num_wrps; ++i) {
700 info = counter_arch_bp(wp);
702 * The DFAR is an unknown value on debug architectures prior
703 * to 7.1. Since we only allow a single watchpoint on these
704 * older CPUs, we can set the trigger to the lowest possible
707 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
709 info->trigger = wp->attr.bp_addr;
711 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
712 alignment_mask = 0x7;
714 alignment_mask = 0x3;
716 /* Check if the watchpoint value matches. */
717 val = read_wb_reg(ARM_BASE_WVR + i);
718 if (val != (addr & ~alignment_mask))
721 /* Possible match, check the byte address select. */
722 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
723 decode_ctrl_reg(ctrl_reg, &ctrl);
724 if (!((1 << (addr & alignment_mask)) & ctrl.len))
727 /* Check that the access type matches. */
728 if (debug_exception_updates_fsr()) {
729 access = (fsr & ARM_FSR_ACCESS_MASK) ?
730 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
731 if (!(access & hw_breakpoint_type(wp)))
735 /* We have a winner. */
736 info->trigger = addr;
739 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
740 perf_bp_event(wp, regs);
743 * If no overflow handler is present, insert a temporary
744 * mismatch breakpoint so we can single-step over the
745 * watchpoint trigger.
747 if (!wp->overflow_handler)
748 enable_single_step(wp, instruction_pointer(regs));
755 static void watchpoint_single_step_handler(unsigned long pc)
758 struct perf_event *wp, **slots;
759 struct arch_hw_breakpoint *info;
761 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
763 for (i = 0; i < core_num_wrps; ++i) {
771 info = counter_arch_bp(wp);
772 if (!info->step_ctrl.enabled)
776 * Restore the original watchpoint if we've completed the
779 if (info->trigger != pc)
780 disable_single_step(wp);
787 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
790 u32 ctrl_reg, val, addr;
791 struct perf_event *bp, **slots;
792 struct arch_hw_breakpoint *info;
793 struct arch_hw_breakpoint_ctrl ctrl;
795 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
797 /* The exception entry code places the amended lr in the PC. */
800 /* Check the currently installed breakpoints first. */
801 for (i = 0; i < core_num_brps; ++i) {
809 info = counter_arch_bp(bp);
811 /* Check if the breakpoint value matches. */
812 val = read_wb_reg(ARM_BASE_BVR + i);
813 if (val != (addr & ~0x3))
816 /* Possible match, check the byte address select to confirm. */
817 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
818 decode_ctrl_reg(ctrl_reg, &ctrl);
819 if ((1 << (addr & 0x3)) & ctrl.len) {
820 info->trigger = addr;
821 pr_debug("breakpoint fired: address = 0x%x\n", addr);
822 perf_bp_event(bp, regs);
823 if (!bp->overflow_handler)
824 enable_single_step(bp, addr);
829 /* If we're stepping a breakpoint, it can now be restored. */
830 if (info->step_ctrl.enabled)
831 disable_single_step(bp);
836 /* Handle any pending watchpoint single-step breakpoints. */
837 watchpoint_single_step_handler(addr);
841 * Called from either the Data Abort Handler [watchpoint] or the
842 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
844 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
845 struct pt_regs *regs)
852 if (interrupts_enabled(regs))
855 /* We only handle watchpoints and hardware breakpoints. */
856 ARM_DBG_READ(c1, 0, dscr);
858 /* Perform perf callbacks. */
859 switch (ARM_DSCR_MOE(dscr)) {
860 case ARM_ENTRY_BREAKPOINT:
861 breakpoint_handler(addr, regs);
863 case ARM_ENTRY_ASYNC_WATCHPOINT:
864 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
865 case ARM_ENTRY_SYNC_WATCHPOINT:
866 watchpoint_handler(addr, fsr, regs);
869 ret = 1; /* Unhandled fault. */
878 * One-time initialisation.
880 static cpumask_t debug_err_mask;
882 static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
884 int cpu = smp_processor_id();
886 pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
889 /* Set the error flag for this CPU and skip the faulting instruction. */
890 cpumask_set_cpu(cpu, &debug_err_mask);
891 instruction_pointer(regs) += 4;
895 static struct undef_hook debug_reg_hook = {
896 .instr_mask = 0x0fe80f10,
897 .instr_val = 0x0e000e10,
898 .fn = debug_reg_trap,
901 static void reset_ctrl_regs(void *unused)
903 int i, raw_num_brps, err = 0, cpu = smp_processor_id();
907 * v7 debug contains save and restore registers so that debug state
908 * can be maintained across low-power modes without leaving the debug
909 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
910 * the debug registers out of reset, so we must unlock the OS Lock
911 * Access Register to avoid taking undefined instruction exceptions
914 switch (debug_arch) {
915 case ARM_DEBUG_ARCH_V6:
916 case ARM_DEBUG_ARCH_V6_1:
917 /* ARMv6 cores clear the registers out of reset. */
919 case ARM_DEBUG_ARCH_V7_ECP14:
921 * Ensure sticky power-down is clear (i.e. debug logic is
924 asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (val));
925 if ((val & 0x1) == 0)
929 * Check whether we implement OS save and restore.
931 asm volatile("mrc p14, 0, %0, c1, c1, 4" : "=r" (val));
932 if ((val & 0x9) == 0)
935 case ARM_DEBUG_ARCH_V7_1:
937 * Ensure the OS double lock is clear.
939 asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (val));
940 if ((val & 0x1) == 1)
946 pr_warning("CPU %d debug is powered down!\n", cpu);
947 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
952 * Unconditionally clear the OS lock by writing a value
953 * other than 0xC5ACCE55 to the access register.
955 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
959 * Clear any configured vector-catch events before
960 * enabling monitor mode.
963 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
966 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
967 pr_warning("CPU %d failed to disable vector catch\n", cpu);
972 * The control/value register pairs are UNKNOWN out of reset so
973 * clear them to avoid spurious debug events.
975 raw_num_brps = get_num_brp_resources();
976 for (i = 0; i < raw_num_brps; ++i) {
977 write_wb_reg(ARM_BASE_BCR + i, 0UL);
978 write_wb_reg(ARM_BASE_BVR + i, 0UL);
981 for (i = 0; i < core_num_wrps; ++i) {
982 write_wb_reg(ARM_BASE_WCR + i, 0UL);
983 write_wb_reg(ARM_BASE_WVR + i, 0UL);
986 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
987 pr_warning("CPU %d failed to clear debug register pairs\n", cpu);
992 * Have a crack at enabling monitor mode. We don't actually need
993 * it yet, but reporting an error early is useful if it fails.
996 if (enable_monitor_mode())
997 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1000 static int __cpuinit dbg_reset_notify(struct notifier_block *self,
1001 unsigned long action, void *cpu)
1003 if (action == CPU_ONLINE)
1004 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
1009 static struct notifier_block __cpuinitdata dbg_reset_nb = {
1010 .notifier_call = dbg_reset_notify,
1013 static int __init arch_hw_breakpoint_init(void)
1015 debug_arch = get_debug_arch();
1017 if (!debug_arch_supported()) {
1018 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1022 /* Determine how many BRPs/WRPs are available. */
1023 core_num_brps = get_num_brps();
1024 core_num_wrps = get_num_wrps();
1027 * We need to tread carefully here because DBGSWENABLE may be
1028 * driven low on this core and there isn't an architected way to
1031 register_undef_hook(&debug_reg_hook);
1034 * Reset the breakpoint resources. We assume that a halting
1035 * debugger will leave the world in a nice state for us.
1037 on_each_cpu(reset_ctrl_regs, NULL, 1);
1038 unregister_undef_hook(&debug_reg_hook);
1039 if (!cpumask_empty(&debug_err_mask)) {
1045 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1046 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1049 /* Work out the maximum supported watchpoint length. */
1050 max_watchpoint_len = get_max_wp_len();
1051 pr_info("maximum watchpoint size is %u bytes.\n",
1052 max_watchpoint_len);
1054 /* Register debug fault handler. */
1055 hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1056 TRAP_HWBKPT, "watchpoint debug exception");
1057 hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1058 TRAP_HWBKPT, "breakpoint debug exception");
1060 /* Register hotplug notifier. */
1061 register_cpu_notifier(&dbg_reset_nb);
1064 arch_initcall(arch_hw_breakpoint_init);
1066 void hw_breakpoint_pmu_read(struct perf_event *bp)
1071 * Dummy function to register with die_notifier.
1073 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1074 unsigned long val, void *data)