2 * arch/arm/include/asm/tlbflush.h
4 * Copyright (C) 1999-2003 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_TLBFLUSH_H
11 #define _ASMARM_TLBFLUSH_H
17 #define TLB_V3_PAGE (1 << 0)
18 #define TLB_V4_U_PAGE (1 << 1)
19 #define TLB_V4_D_PAGE (1 << 2)
20 #define TLB_V4_I_PAGE (1 << 3)
21 #define TLB_V6_U_PAGE (1 << 4)
22 #define TLB_V6_D_PAGE (1 << 5)
23 #define TLB_V6_I_PAGE (1 << 6)
25 #define TLB_V3_FULL (1 << 8)
26 #define TLB_V4_U_FULL (1 << 9)
27 #define TLB_V4_D_FULL (1 << 10)
28 #define TLB_V4_I_FULL (1 << 11)
29 #define TLB_V6_U_FULL (1 << 12)
30 #define TLB_V6_D_FULL (1 << 13)
31 #define TLB_V6_I_FULL (1 << 14)
33 #define TLB_V6_U_ASID (1 << 16)
34 #define TLB_V6_D_ASID (1 << 17)
35 #define TLB_V6_I_ASID (1 << 18)
37 #define TLB_V6_BP (1 << 19)
39 /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
40 #define TLB_V7_UIS_PAGE (1 << 20)
41 #define TLB_V7_UIS_FULL (1 << 21)
42 #define TLB_V7_UIS_ASID (1 << 22)
43 #define TLB_V7_UIS_BP (1 << 23)
45 #define TLB_BARRIER (1 << 28)
46 #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
47 #define TLB_DCLEAN (1 << 30)
48 #define TLB_WB (1 << 31)
54 * We have the following to choose from:
56 * v4 - ARMv4 without write buffer
57 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
58 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
59 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
60 * fa - Faraday (v4 with write buffer with UTLB)
61 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
62 * v7wbi - identical to v6wbi
67 #ifdef CONFIG_SMP_ON_UP
71 #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE)
73 #ifdef CONFIG_CPU_TLB_V4WT
74 # define v4_possible_flags v4_tlb_flags
75 # define v4_always_flags v4_tlb_flags
82 # define v4_possible_flags 0
83 # define v4_always_flags (-1UL)
86 #define fa_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
87 TLB_V4_U_FULL | TLB_V4_U_PAGE)
89 #ifdef CONFIG_CPU_TLB_FA
90 # define fa_possible_flags fa_tlb_flags
91 # define fa_always_flags fa_tlb_flags
98 # define fa_possible_flags 0
99 # define fa_always_flags (-1UL)
102 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
103 TLB_V4_I_FULL | TLB_V4_D_FULL | \
104 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
106 #ifdef CONFIG_CPU_TLB_V4WBI
107 # define v4wbi_possible_flags v4wbi_tlb_flags
108 # define v4wbi_always_flags v4wbi_tlb_flags
115 # define v4wbi_possible_flags 0
116 # define v4wbi_always_flags (-1UL)
119 #define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
120 TLB_V4_I_FULL | TLB_V4_D_FULL | \
121 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
123 #ifdef CONFIG_CPU_TLB_FEROCEON
124 # define fr_possible_flags fr_tlb_flags
125 # define fr_always_flags fr_tlb_flags
132 # define fr_possible_flags 0
133 # define fr_always_flags (-1UL)
136 #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
137 TLB_V4_I_FULL | TLB_V4_D_FULL | \
140 #ifdef CONFIG_CPU_TLB_V4WB
141 # define v4wb_possible_flags v4wb_tlb_flags
142 # define v4wb_always_flags v4wb_tlb_flags
149 # define v4wb_possible_flags 0
150 # define v4wb_always_flags (-1UL)
153 #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
154 TLB_V6_I_FULL | TLB_V6_D_FULL | \
155 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
156 TLB_V6_I_ASID | TLB_V6_D_ASID | \
159 #ifdef CONFIG_CPU_TLB_V6
160 # define v6wbi_possible_flags v6wbi_tlb_flags
161 # define v6wbi_always_flags v6wbi_tlb_flags
168 # define v6wbi_possible_flags 0
169 # define v6wbi_always_flags (-1UL)
172 #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
173 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
174 TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
175 #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
176 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
177 TLB_V6_U_ASID | TLB_V6_BP)
179 #ifdef CONFIG_CPU_TLB_V7
181 # ifdef CONFIG_SMP_ON_UP
182 # define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
183 # define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
184 # elif defined(CONFIG_SMP)
185 # define v7wbi_possible_flags v7wbi_tlb_flags_smp
186 # define v7wbi_always_flags v7wbi_tlb_flags_smp
188 # define v7wbi_possible_flags v7wbi_tlb_flags_up
189 # define v7wbi_always_flags v7wbi_tlb_flags_up
197 # define v7wbi_possible_flags 0
198 # define v7wbi_always_flags (-1UL)
202 #error Unknown TLB model
207 #include <linux/sched.h>
210 void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
211 void (*flush_kern_range)(unsigned long, unsigned long);
212 unsigned long tlb_flags;
216 * Select the calling method
220 #define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
221 #define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
225 #define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
226 #define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
228 extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
229 extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
233 extern struct cpu_tlb_fns cpu_tlb;
235 #define __cpu_tlb_flags cpu_tlb.tlb_flags
241 * The arch/arm/mm/tlb-*.S files implement these methods.
243 * The TLB specific code is expected to perform whatever tests it
244 * needs to determine if it should invalidate the TLB for each
245 * call. Start addresses are inclusive and end addresses are
246 * exclusive; it is safe to round these addresses down.
250 * Invalidate the entire TLB.
254 * Invalidate all TLB entries in a particular address
256 * - mm - mm_struct describing address space
258 * flush_tlb_range(mm,start,end)
260 * Invalidate a range of TLB entries in the specified
262 * - mm - mm_struct describing address space
263 * - start - start address (may not be aligned)
264 * - end - end address (exclusive, may not be aligned)
266 * flush_tlb_page(vaddr,vma)
268 * Invalidate the specified page in the specified address range.
269 * - vaddr - virtual address (may not be aligned)
270 * - vma - vma_struct describing address range
272 * flush_kern_tlb_page(kaddr)
274 * Invalidate the TLB entry for the specified page. The address
275 * will be in the kernels virtual memory space. Current uses
276 * only require the D-TLB to be invalidated.
277 * - kaddr - Kernel virtual memory address
281 * We optimise the code below by:
282 * - building a set of TLB flags that might be set in __cpu_tlb_flags
283 * - building a set of TLB flags that will always be set in __cpu_tlb_flags
284 * - if we're going to need __cpu_tlb_flags, access it once and only once
286 * This allows us to build optimal assembly for the single-CPU type case,
287 * and as close to optimal given the compiler constrants for multi-CPU
288 * case. We could do better for the multi-CPU case if the compiler
289 * implemented the "%?" method, but this has been discontinued due to too
290 * many people getting it wrong.
292 #define possible_tlb_flags (v4_possible_flags | \
293 v4wbi_possible_flags | \
294 fr_possible_flags | \
295 v4wb_possible_flags | \
296 fa_possible_flags | \
297 v6wbi_possible_flags | \
298 v7wbi_possible_flags)
300 #define always_tlb_flags (v4_always_flags & \
301 v4wbi_always_flags & \
303 v4wb_always_flags & \
305 v6wbi_always_flags & \
308 #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
310 #define __tlb_op(f, insnarg, arg) \
312 if (always_tlb_flags & (f)) \
314 : : "r" (arg) : "cc"); \
315 else if (possible_tlb_flags & (f)) \
316 asm("tst %1, %2\n\t" \
318 : : "r" (arg), "r" (__tlb_flag), "Ir" (f) \
322 #define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg)
323 #define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg)
325 static inline void local_flush_tlb_all(void)
328 const unsigned int __tlb_flag = __cpu_tlb_flags;
330 if (tlb_flag(TLB_WB))
333 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
334 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
335 tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
336 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
337 tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
339 if (tlb_flag(TLB_BARRIER)) {
345 static inline void local_flush_tlb_mm(struct mm_struct *mm)
348 const int asid = ASID(mm);
349 const unsigned int __tlb_flag = __cpu_tlb_flags;
351 if (tlb_flag(TLB_WB))
354 if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
355 if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
356 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
357 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
358 tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
359 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
364 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
365 tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
366 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
367 #ifdef CONFIG_ARM_ERRATA_720789
368 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
370 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
373 if (tlb_flag(TLB_BARRIER))
378 local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
381 const unsigned int __tlb_flag = __cpu_tlb_flags;
383 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
385 if (tlb_flag(TLB_WB))
388 if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
389 cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
390 tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);
391 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
392 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
393 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
394 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
395 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
398 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
399 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
400 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
401 #ifdef CONFIG_ARM_ERRATA_720789
402 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
404 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
407 if (tlb_flag(TLB_BARRIER))
411 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
414 const unsigned int __tlb_flag = __cpu_tlb_flags;
418 if (tlb_flag(TLB_WB))
421 tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);
422 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
423 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
424 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
425 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
426 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
428 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
429 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
430 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
431 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
433 if (tlb_flag(TLB_BARRIER)) {
439 static inline void local_flush_bp_all(void)
442 const unsigned int __tlb_flag = __cpu_tlb_flags;
444 if (tlb_flag(TLB_V7_UIS_BP))
445 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
446 else if (tlb_flag(TLB_V6_BP))
447 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
449 if (tlb_flag(TLB_BARRIER))
453 #ifdef CONFIG_ARM_ERRATA_798181
454 static inline void dummy_flush_tlb_a15_erratum(void)
457 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
459 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
463 static inline void dummy_flush_tlb_a15_erratum(void)
471 * Flush a PMD entry (word aligned, or double-word aligned) to
472 * RAM if the TLB for the CPU we are running on requires this.
473 * This is typically used when we are creating PMD entries.
477 * Clean (but don't drain the write buffer) if the CPU requires
478 * these operations. This is typically used when we are removing
481 static inline void flush_pmd_entry(void *pmd)
483 const unsigned int __tlb_flag = __cpu_tlb_flags;
485 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
486 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
488 if (tlb_flag(TLB_WB))
492 static inline void clean_pmd_entry(void *pmd)
494 const unsigned int __tlb_flag = __cpu_tlb_flags;
496 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
497 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
502 #undef always_tlb_flags
503 #undef possible_tlb_flags
506 * Convert calls to our calling convention.
508 #define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
509 #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
512 #define flush_tlb_all local_flush_tlb_all
513 #define flush_tlb_mm local_flush_tlb_mm
514 #define flush_tlb_page local_flush_tlb_page
515 #define flush_tlb_kernel_page local_flush_tlb_kernel_page
516 #define flush_tlb_range local_flush_tlb_range
517 #define flush_tlb_kernel_range local_flush_tlb_kernel_range
518 #define flush_bp_all local_flush_bp_all
520 extern void flush_tlb_all(void);
521 extern void flush_tlb_mm(struct mm_struct *mm);
522 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
523 extern void flush_tlb_kernel_page(unsigned long kaddr);
524 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
525 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
526 extern void flush_bp_all(void);
530 * If PG_dcache_clean is not set for the page, we need to ensure that any
531 * cache entries for the kernels virtual memory range are written
532 * back to the page. On ARMv6 and later, the cache coherency is handled via
533 * the set_pte_at() function.
535 #if __LINUX_ARM_ARCH__ < 6
536 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
539 static inline void update_mmu_cache(struct vm_area_struct *vma,
540 unsigned long addr, pte_t *ptep)
547 #endif /* CONFIG_MMU */