1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
9 #define CR_M (1 << 0) /* MMU enable */
10 #define CR_A (1 << 1) /* Alignment abort enable */
11 #define CR_C (1 << 2) /* Dcache enable */
12 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
13 #define CR_I (1 << 12) /* Icache enable */
14 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
15 #define CR_EE (1 << 25) /* Exception (Big) Endian */
17 #define PGTABLE_SIZE (0x10000)
23 "isb" : : : "memory"); \
28 "wfi" : : : "memory"); \
31 static inline unsigned int current_el(void)
34 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
38 static inline unsigned int get_sctlr(void)
44 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
46 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
48 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
53 static inline void set_sctlr(unsigned int val)
59 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
61 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
63 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
68 void __asm_flush_dcache_all(void);
69 void __asm_invalidate_dcache_all(void);
70 void __asm_flush_dcache_range(u64 start, u64 end);
71 void __asm_invalidate_tlb_all(void);
72 void __asm_invalidate_icache_all(void);
74 void armv8_switch_to_el2(void);
75 void armv8_switch_to_el1(void);
77 void gic_send_sgi(unsigned long sgino);
78 void wait_for_wakeup(void);
79 void smp_kick_all_cpus(void);
81 void flush_l3_cache(void);
83 #endif /* __ASSEMBLY__ */
85 #else /* CONFIG_ARM64 */
89 #define CPU_ARCH_UNKNOWN 0
90 #define CPU_ARCH_ARMv3 1
91 #define CPU_ARCH_ARMv4 2
92 #define CPU_ARCH_ARMv4T 3
93 #define CPU_ARCH_ARMv5 4
94 #define CPU_ARCH_ARMv5T 5
95 #define CPU_ARCH_ARMv5TE 6
96 #define CPU_ARCH_ARMv5TEJ 7
97 #define CPU_ARCH_ARMv6 8
98 #define CPU_ARCH_ARMv7 9
101 * CR1 bits (CP#15 CR1)
103 #define CR_M (1 << 0) /* MMU enable */
104 #define CR_A (1 << 1) /* Alignment abort enable */
105 #define CR_C (1 << 2) /* Dcache enable */
106 #define CR_W (1 << 3) /* Write buffer enable */
107 #define CR_P (1 << 4) /* 32-bit exception handler */
108 #define CR_D (1 << 5) /* 32-bit data address range */
109 #define CR_L (1 << 6) /* Implementation defined */
110 #define CR_B (1 << 7) /* Big endian */
111 #define CR_S (1 << 8) /* System MMU protection */
112 #define CR_R (1 << 9) /* ROM MMU protection */
113 #define CR_F (1 << 10) /* Implementation defined */
114 #define CR_Z (1 << 11) /* Implementation defined */
115 #define CR_I (1 << 12) /* Icache enable */
116 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
117 #define CR_RR (1 << 14) /* Round Robin cache replacement */
118 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
119 #define CR_DT (1 << 16)
120 #define CR_IT (1 << 18)
121 #define CR_ST (1 << 19)
122 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
123 #define CR_U (1 << 22) /* Unaligned access operation */
124 #define CR_XP (1 << 23) /* Extended page tables */
125 #define CR_VE (1 << 24) /* Vectored interrupts */
126 #define CR_EE (1 << 25) /* Exception (Big) Endian */
127 #define CR_TRE (1 << 28) /* TEX remap enable */
128 #define CR_AFE (1 << 29) /* Access flag enable */
129 #define CR_TE (1 << 30) /* Thumb exception enable */
131 #define PGTABLE_SIZE (4096 * 4)
134 * This is used to ensure the compiler did actually allocate the register we
135 * asked it for some inline assembly sequences. Apparently we can't trust
136 * the compiler from one version to another so a bit of paranoia won't hurt.
137 * This string is meant to be concatenated with the inline asm string and
138 * will cause compilation to stop on mismatch.
139 * (for details, see gcc PR 15089)
141 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
146 * save_boot_params() - Save boot parameters before starting reset sequence
148 * If you provide this function it will be called immediately U-Boot starts,
149 * both for SPL and U-Boot proper.
151 * All registers are unchanged from U-Boot entry. No registers need be
154 * This is not a normal C function. There is no stack. Return by branching to
155 * save_boot_params_ret.
157 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
160 #define isb() __asm__ __volatile__ ("" : : : "memory")
162 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
164 #ifdef __ARM_ARCH_7A__
165 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
170 static inline unsigned int get_cr(void)
173 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
177 static inline void set_cr(unsigned int val)
179 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
180 : : "r" (val) : "cc");
184 static inline unsigned int get_dacr(void)
187 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
191 static inline void set_dacr(unsigned int val)
193 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
194 : : "r" (val) : "cc");
198 /* options available for data cache on each page */
201 DCACHE_WRITETHROUGH = 0x1a,
202 DCACHE_WRITEBACK = 0x1e,
203 DCACHE_WRITEALLOC = 0x16,
206 /* Size of an MMU section */
208 MMU_SECTION_SHIFT = 20,
209 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
213 * Change the cache settings for a region.
215 * \param start start address of memory region to change
216 * \param size size of memory region to change
217 * \param option dcache option to select
219 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
220 enum dcache_option option);
223 * Register an update to the page tables, and flush the TLB
225 * \param start start address of update in page table
226 * \param stop stop address of update in page table
228 void mmu_page_table_flush(unsigned long start, unsigned long stop);
230 #ifdef CONFIG_SYS_NONCACHED_MEMORY
231 void noncached_init(void);
232 phys_addr_t noncached_alloc(size_t size, size_t align);
233 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
235 #endif /* __ASSEMBLY__ */
237 #define arch_align_stack(x) (x)
239 #endif /* __KERNEL__ */
241 #endif /* CONFIG_ARM64 */