1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
9 #define CR_M (1 << 0) /* MMU enable */
10 #define CR_A (1 << 1) /* Alignment abort enable */
11 #define CR_C (1 << 2) /* Dcache enable */
12 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
13 #define CR_I (1 << 12) /* Icache enable */
14 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
15 #define CR_EE (1 << 25) /* Exception (Big) Endian */
17 #define PGTABLE_SIZE (0x10000)
23 "isb" : : : "memory"); \
28 "wfi" : : : "memory"); \
31 static inline unsigned int current_el(void)
34 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
38 static inline unsigned int get_sctlr(void)
44 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
46 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
48 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
53 static inline void set_sctlr(unsigned int val)
59 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
61 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
63 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
68 void __asm_flush_dcache_all(void);
69 void __asm_invalidate_dcache_all(void);
70 void __asm_flush_dcache_range(u64 start, u64 end);
71 void __asm_invalidate_tlb_all(void);
72 void __asm_invalidate_icache_all(void);
73 int __asm_flush_l3_cache(void);
75 void armv8_switch_to_el2(void);
76 void armv8_switch_to_el1(void);
78 void gic_send_sgi(unsigned long sgino);
79 void wait_for_wakeup(void);
80 void smp_kick_all_cpus(void);
82 void flush_l3_cache(void);
84 #endif /* __ASSEMBLY__ */
86 #else /* CONFIG_ARM64 */
90 #define CPU_ARCH_UNKNOWN 0
91 #define CPU_ARCH_ARMv3 1
92 #define CPU_ARCH_ARMv4 2
93 #define CPU_ARCH_ARMv4T 3
94 #define CPU_ARCH_ARMv5 4
95 #define CPU_ARCH_ARMv5T 5
96 #define CPU_ARCH_ARMv5TE 6
97 #define CPU_ARCH_ARMv5TEJ 7
98 #define CPU_ARCH_ARMv6 8
99 #define CPU_ARCH_ARMv7 9
102 * CR1 bits (CP#15 CR1)
104 #define CR_M (1 << 0) /* MMU enable */
105 #define CR_A (1 << 1) /* Alignment abort enable */
106 #define CR_C (1 << 2) /* Dcache enable */
107 #define CR_W (1 << 3) /* Write buffer enable */
108 #define CR_P (1 << 4) /* 32-bit exception handler */
109 #define CR_D (1 << 5) /* 32-bit data address range */
110 #define CR_L (1 << 6) /* Implementation defined */
111 #define CR_B (1 << 7) /* Big endian */
112 #define CR_S (1 << 8) /* System MMU protection */
113 #define CR_R (1 << 9) /* ROM MMU protection */
114 #define CR_F (1 << 10) /* Implementation defined */
115 #define CR_Z (1 << 11) /* Implementation defined */
116 #define CR_I (1 << 12) /* Icache enable */
117 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
118 #define CR_RR (1 << 14) /* Round Robin cache replacement */
119 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
120 #define CR_DT (1 << 16)
121 #define CR_IT (1 << 18)
122 #define CR_ST (1 << 19)
123 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
124 #define CR_U (1 << 22) /* Unaligned access operation */
125 #define CR_XP (1 << 23) /* Extended page tables */
126 #define CR_VE (1 << 24) /* Vectored interrupts */
127 #define CR_EE (1 << 25) /* Exception (Big) Endian */
128 #define CR_TRE (1 << 28) /* TEX remap enable */
129 #define CR_AFE (1 << 29) /* Access flag enable */
130 #define CR_TE (1 << 30) /* Thumb exception enable */
132 #define PGTABLE_SIZE (4096 * 4)
135 * This is used to ensure the compiler did actually allocate the register we
136 * asked it for some inline assembly sequences. Apparently we can't trust
137 * the compiler from one version to another so a bit of paranoia won't hurt.
138 * This string is meant to be concatenated with the inline asm string and
139 * will cause compilation to stop on mismatch.
140 * (for details, see gcc PR 15089)
142 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
147 * save_boot_params() - Save boot parameters before starting reset sequence
149 * If you provide this function it will be called immediately U-Boot starts,
150 * both for SPL and U-Boot proper.
152 * All registers are unchanged from U-Boot entry. No registers need be
155 * This is not a normal C function. There is no stack. Return by branching to
156 * save_boot_params_ret.
158 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
161 #define isb() __asm__ __volatile__ ("" : : : "memory")
163 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
165 #ifdef __ARM_ARCH_7A__
166 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
171 static inline unsigned int get_cr(void)
174 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
178 static inline void set_cr(unsigned int val)
180 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
181 : : "r" (val) : "cc");
185 static inline unsigned int get_dacr(void)
188 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
192 static inline void set_dacr(unsigned int val)
194 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
195 : : "r" (val) : "cc");
200 /* Short-Descriptor Translation Table Level 1 Bits */
201 #define TTB_SECT_NS_MASK (1 << 19)
202 #define TTB_SECT_NG_MASK (1 << 17)
203 #define TTB_SECT_S_MASK (1 << 16)
204 /* Note: TTB AP bits are set elsewhere */
205 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
206 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
207 #define TTB_SECT_XN_MASK (1 << 4)
208 #define TTB_SECT_C_MASK (1 << 3)
209 #define TTB_SECT_B_MASK (1 << 2)
210 #define TTB_SECT (2 << 0)
212 /* options available for data cache on each page */
214 DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
215 TTB_SECT_XN_MASK | TTB_SECT,
216 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
217 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
218 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
221 /* options available for data cache on each page */
224 DCACHE_WRITETHROUGH = 0x1a,
225 DCACHE_WRITEBACK = 0x1e,
226 DCACHE_WRITEALLOC = 0x16,
230 /* Size of an MMU section */
232 MMU_SECTION_SHIFT = 20,
233 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
238 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
239 #define TTBR0_RGN_NC (0 << 3)
240 #define TTBR0_RGN_WBWA (1 << 3)
241 #define TTBR0_RGN_WT (2 << 3)
242 #define TTBR0_RGN_WB (3 << 3)
243 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
244 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
245 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
246 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
247 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
251 * Change the cache settings for a region.
253 * \param start start address of memory region to change
254 * \param size size of memory region to change
255 * \param option dcache option to select
257 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
258 enum dcache_option option);
261 * Register an update to the page tables, and flush the TLB
263 * \param start start address of update in page table
264 * \param stop stop address of update in page table
266 void mmu_page_table_flush(unsigned long start, unsigned long stop);
268 #ifdef CONFIG_SYS_NONCACHED_MEMORY
269 void noncached_init(void);
270 phys_addr_t noncached_alloc(size_t size, size_t align);
271 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
273 #endif /* __ASSEMBLY__ */
275 #define arch_align_stack(x) (x)
277 #endif /* __KERNEL__ */
279 #endif /* CONFIG_ARM64 */