arch/arm/include/asm/omap_common.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Aneesh V <aneesh@ti.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25 #ifndef _OMAP_COMMON_H_
  26 #define _OMAP_COMMON_H_
  27
  28 #include <common.h>
  29
  30 struct prcm_regs {
  31         /* cm1.ckgen */
  32         u32 cm_clksel_core;
  33         u32 cm_clksel_abe;
  34         u32 cm_dll_ctrl;
  35         u32 cm_clkmode_dpll_core;
  36         u32 cm_idlest_dpll_core;
  37         u32 cm_autoidle_dpll_core;
  38         u32 cm_clksel_dpll_core;
  39         u32 cm_div_m2_dpll_core;
  40         u32 cm_div_m3_dpll_core;
  41         u32 cm_div_h11_dpll_core;
  42         u32 cm_div_h12_dpll_core;
  43         u32 cm_div_h13_dpll_core;
  44         u32 cm_div_h14_dpll_core;
  45         u32 cm_ssc_deltamstep_dpll_core;
  46         u32 cm_ssc_modfreqdiv_dpll_core;
  47         u32 cm_emu_override_dpll_core;
  48         u32 cm_div_h22_dpllcore;
  49         u32 cm_div_h23_dpll_core;
  50         u32 cm_clkmode_dpll_mpu;
  51         u32 cm_idlest_dpll_mpu;
  52         u32 cm_autoidle_dpll_mpu;
  53         u32 cm_clksel_dpll_mpu;
  54         u32 cm_div_m2_dpll_mpu;
  55         u32 cm_ssc_deltamstep_dpll_mpu;
  56         u32 cm_ssc_modfreqdiv_dpll_mpu;
  57         u32 cm_bypclk_dpll_mpu;
  58         u32 cm_clkmode_dpll_iva;
  59         u32 cm_idlest_dpll_iva;
  60         u32 cm_autoidle_dpll_iva;
  61         u32 cm_clksel_dpll_iva;
  62         u32 cm_div_h11_dpll_iva;
  63         u32 cm_div_h12_dpll_iva;
  64         u32 cm_ssc_deltamstep_dpll_iva;
  65         u32 cm_ssc_modfreqdiv_dpll_iva;
  66         u32 cm_bypclk_dpll_iva;
  67         u32 cm_clkmode_dpll_abe;
  68         u32 cm_idlest_dpll_abe;
  69         u32 cm_autoidle_dpll_abe;
  70         u32 cm_clksel_dpll_abe;
  71         u32 cm_div_m2_dpll_abe;
  72         u32 cm_div_m3_dpll_abe;
  73         u32 cm_ssc_deltamstep_dpll_abe;
  74         u32 cm_ssc_modfreqdiv_dpll_abe;
  75         u32 cm_clkmode_dpll_ddrphy;
  76         u32 cm_idlest_dpll_ddrphy;
  77         u32 cm_autoidle_dpll_ddrphy;
  78         u32 cm_clksel_dpll_ddrphy;
  79         u32 cm_div_m2_dpll_ddrphy;
  80         u32 cm_div_h11_dpll_ddrphy;
  81         u32 cm_div_h12_dpll_ddrphy;
  82         u32 cm_div_h13_dpll_ddrphy;
  83         u32 cm_ssc_deltamstep_dpll_ddrphy;
  84         u32 cm_shadow_freq_config1;
  85         u32 cm_mpu_mpu_clkctrl;
  86
  87         /* cm1.dsp */
  88         u32 cm_dsp_clkstctrl;
  89         u32 cm_dsp_dsp_clkctrl;
  90
  91         /* cm1.abe */
  92         u32 cm1_abe_clkstctrl;
  93         u32 cm1_abe_l4abe_clkctrl;
  94         u32 cm1_abe_aess_clkctrl;
  95         u32 cm1_abe_pdm_clkctrl;
  96         u32 cm1_abe_dmic_clkctrl;
  97         u32 cm1_abe_mcasp_clkctrl;
  98         u32 cm1_abe_mcbsp1_clkctrl;
  99         u32 cm1_abe_mcbsp2_clkctrl;
 100         u32 cm1_abe_mcbsp3_clkctrl;
 101         u32 cm1_abe_slimbus_clkctrl;
 102         u32 cm1_abe_timer5_clkctrl;
 103         u32 cm1_abe_timer6_clkctrl;
 104         u32 cm1_abe_timer7_clkctrl;
 105         u32 cm1_abe_timer8_clkctrl;
 106         u32 cm1_abe_wdt3_clkctrl;
 107
 108         /* cm2.ckgen */
 109         u32 cm_clksel_mpu_m3_iss_root;
 110         u32 cm_clksel_usb_60mhz;
 111         u32 cm_scale_fclk;
 112         u32 cm_core_dvfs_perf1;
 113         u32 cm_core_dvfs_perf2;
 114         u32 cm_core_dvfs_perf3;
 115         u32 cm_core_dvfs_perf4;
 116         u32 cm_core_dvfs_current;
 117         u32 cm_iva_dvfs_perf_tesla;
 118         u32 cm_iva_dvfs_perf_ivahd;
 119         u32 cm_iva_dvfs_perf_abe;
 120         u32 cm_iva_dvfs_current;
 121         u32 cm_clkmode_dpll_per;
 122         u32 cm_idlest_dpll_per;
 123         u32 cm_autoidle_dpll_per;
 124         u32 cm_clksel_dpll_per;
 125         u32 cm_div_m2_dpll_per;
 126         u32 cm_div_m3_dpll_per;
 127         u32 cm_div_h11_dpll_per;
 128         u32 cm_div_h12_dpll_per;
 129         u32 cm_div_h14_dpll_per;
 130         u32 cm_ssc_deltamstep_dpll_per;
 131         u32 cm_ssc_modfreqdiv_dpll_per;
 132         u32 cm_emu_override_dpll_per;
 133         u32 cm_clkmode_dpll_usb;
 134         u32 cm_idlest_dpll_usb;
 135         u32 cm_autoidle_dpll_usb;
 136         u32 cm_clksel_dpll_usb;
 137         u32 cm_div_m2_dpll_usb;
 138         u32 cm_ssc_deltamstep_dpll_usb;
 139         u32 cm_ssc_modfreqdiv_dpll_usb;
 140         u32 cm_clkdcoldo_dpll_usb;
 141         u32 cm_clkmode_dpll_unipro;
 142         u32 cm_idlest_dpll_unipro;
 143         u32 cm_autoidle_dpll_unipro;
 144         u32 cm_clksel_dpll_unipro;
 145         u32 cm_div_m2_dpll_unipro;
 146         u32 cm_ssc_deltamstep_dpll_unipro;
 147         u32 cm_ssc_modfreqdiv_dpll_unipro;
 148
 149         /* cm2.core */
 150         u32 cm_coreaon_bandgap_clkctrl;
 151         u32 cm_l3_1_clkstctrl;
 152         u32 cm_l3_1_dynamicdep;
 153         u32 cm_l3_1_l3_1_clkctrl;
 154         u32 cm_l3_2_clkstctrl;
 155         u32 cm_l3_2_dynamicdep;
 156         u32 cm_l3_2_l3_2_clkctrl;
 157         u32 cm_l3_2_gpmc_clkctrl;
 158         u32 cm_l3_2_ocmc_ram_clkctrl;
 159         u32 cm_mpu_m3_clkstctrl;
 160         u32 cm_mpu_m3_staticdep;
 161         u32 cm_mpu_m3_dynamicdep;
 162         u32 cm_mpu_m3_mpu_m3_clkctrl;
 163         u32 cm_sdma_clkstctrl;
 164         u32 cm_sdma_staticdep;
 165         u32 cm_sdma_dynamicdep;
 166         u32 cm_sdma_sdma_clkctrl;
 167         u32 cm_memif_clkstctrl;
 168         u32 cm_memif_dmm_clkctrl;
 169         u32 cm_memif_emif_fw_clkctrl;
 170         u32 cm_memif_emif_1_clkctrl;
 171         u32 cm_memif_emif_2_clkctrl;
 172         u32 cm_memif_dll_clkctrl;
 173         u32 cm_memif_emif_h1_clkctrl;
 174         u32 cm_memif_emif_h2_clkctrl;
 175         u32 cm_memif_dll_h_clkctrl;
 176         u32 cm_c2c_clkstctrl;
 177         u32 cm_c2c_staticdep;
 178         u32 cm_c2c_dynamicdep;
 179         u32 cm_c2c_sad2d_clkctrl;
 180         u32 cm_c2c_modem_icr_clkctrl;
 181         u32 cm_c2c_sad2d_fw_clkctrl;
 182         u32 cm_l4cfg_clkstctrl;
 183         u32 cm_l4cfg_dynamicdep;
 184         u32 cm_l4cfg_l4_cfg_clkctrl;
 185         u32 cm_l4cfg_hw_sem_clkctrl;
 186         u32 cm_l4cfg_mailbox_clkctrl;
 187         u32 cm_l4cfg_sar_rom_clkctrl;
 188         u32 cm_l3instr_clkstctrl;
 189         u32 cm_l3instr_l3_3_clkctrl;
 190         u32 cm_l3instr_l3_instr_clkctrl;
 191         u32 cm_l3instr_intrconn_wp1_clkctrl;
 192
 193         /* cm2.ivahd */
 194         u32 cm_ivahd_clkstctrl;
 195         u32 cm_ivahd_ivahd_clkctrl;
 196         u32 cm_ivahd_sl2_clkctrl;
 197
 198         /* cm2.cam */
 199         u32 cm_cam_clkstctrl;
 200         u32 cm_cam_iss_clkctrl;
 201         u32 cm_cam_fdif_clkctrl;
 202
 203         /* cm2.dss */
 204         u32 cm_dss_clkstctrl;
 205         u32 cm_dss_dss_clkctrl;
 206
 207         /* cm2.sgx */
 208         u32 cm_sgx_clkstctrl;
 209         u32 cm_sgx_sgx_clkctrl;
 210
 211         /* cm2.l3init */
 212         u32 cm_l3init_clkstctrl;
 213
 214         /* cm2.l3init */
 215         u32 cm_l3init_hsmmc1_clkctrl;
 216         u32 cm_l3init_hsmmc2_clkctrl;
 217         u32 cm_l3init_hsi_clkctrl;
 218         u32 cm_l3init_hsusbhost_clkctrl;
 219         u32 cm_l3init_hsusbotg_clkctrl;
 220         u32 cm_l3init_hsusbtll_clkctrl;
 221         u32 cm_l3init_p1500_clkctrl;
 222         u32 cm_l3init_fsusb_clkctrl;
 223         u32 cm_l3init_ocp2scp1_clkctrl;
 224
 225         /* cm2.l4per */
 226         u32 cm_l4per_clkstctrl;
 227         u32 cm_l4per_dynamicdep;
 228         u32 cm_l4per_adc_clkctrl;
 229         u32 cm_l4per_gptimer10_clkctrl;
 230         u32 cm_l4per_gptimer11_clkctrl;
 231         u32 cm_l4per_gptimer2_clkctrl;
 232         u32 cm_l4per_gptimer3_clkctrl;
 233         u32 cm_l4per_gptimer4_clkctrl;
 234         u32 cm_l4per_gptimer9_clkctrl;
 235         u32 cm_l4per_elm_clkctrl;
 236         u32 cm_l4per_gpio2_clkctrl;
 237         u32 cm_l4per_gpio3_clkctrl;
 238         u32 cm_l4per_gpio4_clkctrl;
 239         u32 cm_l4per_gpio5_clkctrl;
 240         u32 cm_l4per_gpio6_clkctrl;
 241         u32 cm_l4per_hdq1w_clkctrl;
 242         u32 cm_l4per_hecc1_clkctrl;
 243         u32 cm_l4per_hecc2_clkctrl;
 244         u32 cm_l4per_i2c1_clkctrl;
 245         u32 cm_l4per_i2c2_clkctrl;
 246         u32 cm_l4per_i2c3_clkctrl;
 247         u32 cm_l4per_i2c4_clkctrl;
 248         u32 cm_l4per_l4per_clkctrl;
 249         u32 cm_l4per_mcasp2_clkctrl;
 250         u32 cm_l4per_mcasp3_clkctrl;
 251         u32 cm_l4per_mgate_clkctrl;
 252         u32 cm_l4per_mcspi1_clkctrl;
 253         u32 cm_l4per_mcspi2_clkctrl;
 254         u32 cm_l4per_mcspi3_clkctrl;
 255         u32 cm_l4per_mcspi4_clkctrl;
 256         u32 cm_l4per_gpio7_clkctrl;
 257         u32 cm_l4per_gpio8_clkctrl;
 258         u32 cm_l4per_mmcsd3_clkctrl;
 259         u32 cm_l4per_mmcsd4_clkctrl;
 260         u32 cm_l4per_msprohg_clkctrl;
 261         u32 cm_l4per_slimbus2_clkctrl;
 262         u32 cm_l4per_uart1_clkctrl;
 263         u32 cm_l4per_uart2_clkctrl;
 264         u32 cm_l4per_uart3_clkctrl;
 265         u32 cm_l4per_uart4_clkctrl;
 266         u32 cm_l4per_mmcsd5_clkctrl;
 267         u32 cm_l4per_i2c5_clkctrl;
 268         u32 cm_l4per_uart5_clkctrl;
 269         u32 cm_l4per_uart6_clkctrl;
 270         u32 cm_l4sec_clkstctrl;
 271         u32 cm_l4sec_staticdep;
 272         u32 cm_l4sec_dynamicdep;
 273         u32 cm_l4sec_aes1_clkctrl;
 274         u32 cm_l4sec_aes2_clkctrl;
 275         u32 cm_l4sec_des3des_clkctrl;
 276         u32 cm_l4sec_pkaeip29_clkctrl;
 277         u32 cm_l4sec_rng_clkctrl;
 278         u32 cm_l4sec_sha2md51_clkctrl;
 279         u32 cm_l4sec_cryptodma_clkctrl;
 280
 281         /* l4 wkup regs */
 282         u32 cm_abe_pll_ref_clksel;
 283         u32 cm_sys_clksel;
 284         u32 cm_wkup_clkstctrl;
 285         u32 cm_wkup_l4wkup_clkctrl;
 286         u32 cm_wkup_wdtimer1_clkctrl;
 287         u32 cm_wkup_wdtimer2_clkctrl;
 288         u32 cm_wkup_gpio1_clkctrl;
 289         u32 cm_wkup_gptimer1_clkctrl;
 290         u32 cm_wkup_gptimer12_clkctrl;
 291         u32 cm_wkup_synctimer_clkctrl;
 292         u32 cm_wkup_usim_clkctrl;
 293         u32 cm_wkup_sarram_clkctrl;
 294         u32 cm_wkup_keyboard_clkctrl;
 295         u32 cm_wkup_rtc_clkctrl;
 296         u32 cm_wkup_bandgap_clkctrl;
 297         u32 cm_wkupaon_scrm_clkctrl;
 298         u32 prm_vc_val_bypass;
 299         u32 prm_vc_cfg_i2c_mode;
 300         u32 prm_vc_cfg_i2c_clk;
 301         u32 prm_sldo_core_setup;
 302         u32 prm_sldo_core_ctrl;
 303         u32 prm_sldo_mpu_setup;
 304         u32 prm_sldo_mpu_ctrl;
 305         u32 prm_sldo_mm_setup;
 306         u32 prm_sldo_mm_ctrl;
 307
 308         u32 cm_div_m4_dpll_core;
 309         u32 cm_div_m5_dpll_core;
 310         u32 cm_div_m6_dpll_core;
 311         u32 cm_div_m7_dpll_core;
 312         u32 cm_div_m4_dpll_iva;
 313         u32 cm_div_m5_dpll_iva;
 314         u32 cm_div_m4_dpll_ddrphy;
 315         u32 cm_div_m5_dpll_ddrphy;
 316         u32 cm_div_m6_dpll_ddrphy;
 317         u32 cm_div_m4_dpll_per;
 318         u32 cm_div_m5_dpll_per;
 319         u32 cm_div_m6_dpll_per;
 320         u32 cm_div_m7_dpll_per;
 321         u32 cm_l3instr_intrconn_wp1_clkct;
 322         u32 cm_l3init_usbphy_clkctrl;
 323         u32 cm_l4per_mcbsp4_clkctrl;
 324         u32 prm_vc_cfg_channel;
 325 };
 326
 327 extern struct prcm_regs const **prcm;
 328 extern struct prcm_regs const omap5_es1_prcm;
 329 extern struct prcm_regs const omap4_prcm;
 330
 331 void hw_data_init(void);
 332 /* Max value for DPLL multiplier M */
 333 #define OMAP_DPLL_MAX_N 127
 334
 335 /* HW Init Context */
 336 #define OMAP_INIT_CONTEXT_SPL                   0
 337 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR        1
 338 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL       2
 339 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH        3
 340
 341 static inline u32 omap_revision(void)
 342 {
 343         extern u32 *const omap_si_rev;
 344         return *omap_si_rev;
 345 }
 346
 347 /*
 348  * silicon revisions.
 349  * Moving this to common, so that most of code can be moved to common,
 350  * directories.
 351  */
 352
 353 /* omap4 */
 354 #define OMAP4430_SILICON_ID_INVALID     0xFFFFFFFF
 355 #define OMAP4430_ES1_0  0x44300100
 356 #define OMAP4430_ES2_0  0x44300200
 357 #define OMAP4430_ES2_1  0x44300210
 358 #define OMAP4430_ES2_2  0x44300220
 359 #define OMAP4430_ES2_3  0x44300230
 360 #define OMAP4460_ES1_0  0x44600100
 361 #define OMAP4460_ES1_1  0x44600110
 362
 363 /* omap5 */
 364 #define OMAP5430_SILICON_ID_INVALID     0
 365 #define OMAP5430_ES1_0  0x54300100
 366 #define OMAP5432_ES1_0  0x54320100
 367 #endif /* _OMAP_COMMON_H_ */