1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
11 #include <asm/mach-imx/regs-common.h>
12 #include <asm/mach-imx/module_fuse.h>
13 #include <linux/bitops.h>
14 #include "../arch-imx/cpu.h"
18 #define soc_rev() (get_cpu_rev() & 0xFF)
19 #define is_soc_rev(rev) (soc_rev() == rev)
21 /* returns MXC_CPU_ value */
22 #define cpu_type(rev) (((rev) >> 12) & 0x1ff)
23 #define soc_type(rev) (((rev) >> 12) & 0xf0)
24 /* both macros return/take MXC_CPU_ constants */
25 #define get_cpu_type() (cpu_type(get_cpu_rev()))
26 #define get_soc_type() (soc_type(get_cpu_rev()))
27 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
28 #define is_soc_type(soc) (get_soc_type() == soc)
30 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
31 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
32 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
33 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
34 #define is_imx9() (is_soc_type(MXC_SOC_IMX9))
35 #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
37 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
38 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
39 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
40 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
41 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
42 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
43 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
44 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
45 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
46 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
47 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
49 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
51 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
52 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
53 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
54 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
55 #define is_imx8ulp() (is_cpu_type(MXC_CPU_IMX8ULP))
56 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
57 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
58 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
59 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
60 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
61 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
62 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
63 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
64 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
65 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
66 is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
67 is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
68 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
69 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
70 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
71 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
72 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
73 #define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
74 #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
75 #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
76 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
77 is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL))
78 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
79 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
80 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
81 #define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL))
83 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
85 #define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \
86 is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
87 is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
88 is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
89 #define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
90 #define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
91 #define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
92 #define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322))
93 #define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
94 #define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
95 #define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
97 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
98 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
101 #define IMX6_SRC_GPR10_BMODE BIT(28)
102 #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
104 #define IMX6_BMODE_MASK GENMASK(7, 0)
105 #define IMX6_BMODE_SHIFT 4
106 #define IMX6_BMODE_EIM_MASK BIT(3)
107 #define IMX6_BMODE_EIM_SHIFT 3
108 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
109 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24
111 enum imx6_bmode_serial_rom {
122 enum imx6_bmode_eim {
129 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
136 IMX6_BMODE_SERIAL_ROM,
142 IMX6_BMODE_NAND_MAX = 0xf,
145 u32 imx6_src_get_boot_mode(void);
148 #endif /* CONFIG_MX6 */
151 #define IMX7_SRC_GPR10_BMODE BIT(28)
152 #define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
155 /* address translation table */
157 u32 da; /* device address (From Cortex M4 view) */
158 u32 sa; /* system bus address */
159 u32 size; /* size of reg range */
162 const struct rproc_att *imx_bootaux_get_hostmap(void);
168 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
169 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
172 enum boot_dev_type_e {
175 BT_DEV_TYPE_NAND = 3,
176 BT_DEV_TYPE_FLEXSPINOR = 4,
177 BT_DEV_TYPE_SPI_NOR = 6,
179 BT_DEV_TYPE_USB = 0xE,
180 BT_DEV_TYPE_MEM_DEV = 0xF,
182 BT_DEV_TYPE_INVALID = 0xFF
185 enum boot_stage_type {
186 BT_STAGE_PRIMARY = 0x6,
187 BT_STAGE_SECONDARY = 0x9,
188 BT_STAGE_RECOVERY = 0xa,
192 #define QUERY_ROM_VER 1
193 #define QUERY_BT_DEV 2
194 #define QUERY_PAGE_SZ 3
195 #define QUERY_IVT_OFF 4
196 #define QUERY_BT_STAGE 5
197 #define QUERY_IMG_OFF 6
199 #define ROM_API_OKAY 0xF0
201 extern struct rom_api *g_rom_api;
202 extern unsigned long rom_pointer[];
204 ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
205 ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
207 u32 rom_api_download_image(u8 *dest, u32 offset, u32 size);
208 u32 rom_api_query_boot_infor(u32 info_type, u32 *info);
211 #define BT0CFG_LPBOOT_MASK 0x1
212 #define BT0CFG_DUALBOOT_MASK 0x2
215 LOW_POWER_BOOT, /* LP_BT = 1 */
216 DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */
217 SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */
220 u32 get_nr_cpus(void);
221 u32 get_cpu_rev(void);
222 u32 get_cpu_speed_grade_hz(void);
223 u32 get_cpu_temp_grade(int *minc, int *maxc);
224 const char *get_imx_type(u32 imxtype);
225 u32 imx_ddr_size(void);
226 void sdelay(unsigned long);
227 void set_chipselect_size(int const);
229 void init_aips(void);
231 void init_snvs(void);
232 void imx_wdog_disable_powerdown(void);
234 void board_mem_get_layout(u64 *phys_sdram_1_start,
235 u64 *phys_sdram_1_size,
236 u64 *phys_sdram_2_start,
237 u64 *phys_sdram_2_size);
239 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
240 int arch_auxiliary_core_check_up(u32 core_id);
242 int board_mmc_get_env_dev(int devno);
244 int nxp_board_rev(void);
245 char nxp_board_rev_string(void);
248 * Initializes on-chip ethernet controllers.
249 * to override, implement board_eth_init()
251 int fecmxc_initialize(struct bd_info *bis);
252 u32 get_ahb_clk(void);
253 u32 get_periph_clk(void);
255 void lcdif_power_down(void);
257 int mxs_reset_block(struct mxs_register_32 *reg);
258 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
259 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
261 void board_late_mmc_env_init(void);
263 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
264 unsigned long reg1, unsigned long reg2,
266 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
267 unsigned long *reg1, unsigned long reg2,
270 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
272 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
273 void enable_ca7_smp(void);
276 enum boot_device get_boot_device(void);