1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
11 #include <asm/mach-imx/regs-common.h>
13 #include "../arch-imx/cpu.h"
15 #define soc_rev() (get_cpu_rev() & 0xFF)
16 #define is_soc_rev(rev) (soc_rev() == rev)
18 /* returns MXC_CPU_ value */
19 #define cpu_type(rev) (((rev) >> 12) & 0xff)
20 #define soc_type(rev) (((rev) >> 12) & 0xf0)
21 /* both macros return/take MXC_CPU_ constants */
22 #define get_cpu_type() (cpu_type(get_cpu_rev()))
23 #define get_soc_type() (soc_type(get_cpu_rev()))
24 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
25 #define is_soc_type(soc) (get_soc_type() == soc)
27 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
28 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
29 #define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
30 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
32 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
33 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
34 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
35 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
36 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
37 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
38 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
39 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
40 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
41 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
43 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
45 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
48 #define IMX6_SRC_GPR10_BMODE BIT(28)
50 #define IMX6_BMODE_MASK GENMASK(7, 0)
51 #define IMX6_BMODE_SHIFT 4
52 #define IMX6_BMODE_EMI_MASK BIT(3)
53 #define IMX6_BMODE_EMI_SHIFT 3
54 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
55 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24
57 enum imx6_bmode_serial_rom {
75 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
82 IMX6_BMODE_SERIAL_ROM,
88 IMX6_BMODE_NAND_MAX = 0xf,
91 static inline u8 imx6_is_bmode_from_gpr9(void)
93 return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
96 u32 imx6_src_get_boot_mode(void);
99 #endif /* CONFIG_MX6 */
101 u32 get_nr_cpus(void);
102 u32 get_cpu_rev(void);
103 u32 get_cpu_speed_grade_hz(void);
104 u32 get_cpu_temp_grade(int *minc, int *maxc);
105 const char *get_imx_type(u32 imxtype);
106 u32 imx_ddr_size(void);
107 void sdelay(unsigned long);
108 void set_chipselect_size(int const);
110 void init_aips(void);
112 void init_snvs(void);
113 void imx_wdog_disable_powerdown(void);
115 int board_mmc_get_env_dev(int devno);
117 int nxp_board_rev(void);
118 char nxp_board_rev_string(void);
121 * Initializes on-chip ethernet controllers.
122 * to override, implement board_eth_init()
124 int fecmxc_initialize(bd_t *bis);
125 u32 get_ahb_clk(void);
126 u32 get_periph_clk(void);
128 void lcdif_power_down(void);
130 int mxs_reset_block(struct mxs_register_32 *reg);
131 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
132 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
134 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
135 unsigned long reg1, unsigned long reg2);