1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
11 #include <asm/mach-imx/regs-common.h>
13 #include "../arch-imx/cpu.h"
15 #define soc_rev() (get_cpu_rev() & 0xFF)
16 #define is_soc_rev(rev) (soc_rev() == rev)
18 /* returns MXC_CPU_ value */
19 #define cpu_type(rev) (((rev) >> 12) & 0x1ff)
20 #define soc_type(rev) (((rev) >> 12) & 0xf0)
21 /* both macros return/take MXC_CPU_ constants */
22 #define get_cpu_type() (cpu_type(get_cpu_rev()))
23 #define get_soc_type() (soc_type(get_cpu_rev()))
24 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
25 #define is_soc_type(soc) (get_soc_type() == soc)
27 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
28 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
29 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
30 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
32 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
33 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
34 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
35 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
36 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
37 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
38 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
39 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
40 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
41 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
42 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
44 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
46 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
47 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
48 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
49 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
50 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
51 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
52 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
53 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
54 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
55 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
56 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
57 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
58 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
59 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
60 is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL))
61 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
62 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
63 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
64 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
65 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
66 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP))
68 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
71 #define IMX6_SRC_GPR10_BMODE BIT(28)
73 #define IMX6_BMODE_MASK GENMASK(7, 0)
74 #define IMX6_BMODE_SHIFT 4
75 #define IMX6_BMODE_EMI_MASK BIT(3)
76 #define IMX6_BMODE_EMI_SHIFT 3
77 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
78 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24
80 enum imx6_bmode_serial_rom {
98 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
105 IMX6_BMODE_SERIAL_ROM,
111 IMX6_BMODE_NAND_MAX = 0xf,
114 u32 imx6_src_get_boot_mode(void);
117 #endif /* CONFIG_MX6 */
119 /* address translation table */
121 u32 da; /* device address (From Cortex M4 view) */
122 u32 sa; /* system bus address */
123 u32 size; /* size of reg range */
131 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
132 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
135 enum boot_dev_type_e {
138 BT_DEV_TYPE_NAND = 3,
139 BT_DEV_TYPE_FLEXSPINOR = 4,
141 BT_DEV_TYPE_USB = 0xE,
142 BT_DEV_TYPE_MEM_DEV = 0xF,
144 BT_DEV_TYPE_INVALID = 0xFF
147 #define QUERY_ROM_VER 1
148 #define QUERY_BT_DEV 2
149 #define QUERY_PAGE_SZ 3
150 #define QUERY_IVT_OFF 4
151 #define QUERY_BT_STAGE 5
152 #define QUERY_IMG_OFF 6
154 #define ROM_API_OKAY 0xF0
156 extern struct rom_api *g_rom_api;
159 u32 get_nr_cpus(void);
160 u32 get_cpu_rev(void);
161 u32 get_cpu_speed_grade_hz(void);
162 u32 get_cpu_temp_grade(int *minc, int *maxc);
163 const char *get_imx_type(u32 imxtype);
164 u32 imx_ddr_size(void);
165 void sdelay(unsigned long);
166 void set_chipselect_size(int const);
168 void init_aips(void);
170 void init_snvs(void);
171 void imx_wdog_disable_powerdown(void);
173 int arch_auxiliary_core_check_up(u32 core_id);
175 int board_mmc_get_env_dev(int devno);
177 int nxp_board_rev(void);
178 char nxp_board_rev_string(void);
181 * Initializes on-chip ethernet controllers.
182 * to override, implement board_eth_init()
184 int fecmxc_initialize(bd_t *bis);
185 u32 get_ahb_clk(void);
186 u32 get_periph_clk(void);
188 void lcdif_power_down(void);
190 int mxs_reset_block(struct mxs_register_32 *reg);
191 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
192 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
194 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
195 unsigned long reg1, unsigned long reg2,
197 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
198 unsigned long *reg1, unsigned long reg2,