1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Freescale i.MX28 APBH DMA
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
8 * Based on code from LTIB:
9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
15 #include <linux/list.h>
16 #include <linux/compiler.h>
18 #define DMA_PIO_WORDS 15
19 #define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
24 #if defined(CONFIG_MX23)
26 MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
27 MXS_DMA_CHANNEL_AHB_APBH_SSP0,
28 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
29 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
30 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
31 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
32 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
33 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
36 #elif defined(CONFIG_MX28)
38 MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
39 MXS_DMA_CHANNEL_AHB_APBH_SSP1,
40 MXS_DMA_CHANNEL_AHB_APBH_SSP2,
41 MXS_DMA_CHANNEL_AHB_APBH_SSP3,
42 MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
43 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
44 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
45 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
46 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
47 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
48 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
49 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
50 MXS_DMA_CHANNEL_AHB_APBH_HSADC,
51 MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
52 MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
53 MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
56 #elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
58 MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
59 MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
60 MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
61 MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
62 MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
63 MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
64 MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
65 MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
71 * MXS DMA hardware command.
73 * This structure describes the in-memory layout of an entire DMA command,
74 * including space for the maximum number of PIO accesses. See the appropriate
75 * reference manual for a detailed description of what these fields mean to the
78 #define MXS_DMA_DESC_COMMAND_MASK 0x3
79 #define MXS_DMA_DESC_COMMAND_OFFSET 0
80 #define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
81 #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
82 #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
83 #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
84 #define MXS_DMA_DESC_CHAIN (1 << 2)
85 #define MXS_DMA_DESC_IRQ (1 << 3)
86 #define MXS_DMA_DESC_NAND_LOCK (1 << 4)
87 #define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
88 #define MXS_DMA_DESC_DEC_SEM (1 << 6)
89 #define MXS_DMA_DESC_WAIT4END (1 << 7)
90 #define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
91 #define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
92 #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
93 #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
94 #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
95 #define MXS_DMA_DESC_BYTES_OFFSET 16
102 unsigned long alternate;
104 unsigned long pio_words[DMA_PIO_WORDS];
108 * MXS DMA command descriptor.
110 * This structure incorporates an MXS DMA hardware command structure, along
113 #define MXS_DMA_DESC_FIRST (1 << 0)
114 #define MXS_DMA_DESC_LAST (1 << 1)
115 #define MXS_DMA_DESC_READY (1 << 31)
117 struct mxs_dma_desc {
118 struct mxs_dma_cmd cmd;
122 struct list_head node;
123 } __aligned(MXS_DMA_ALIGNMENT);
128 * This structure represents a single DMA channel. The MXS platform code
129 * maintains an array of these structures to represent every DMA channel in the
130 * system (see mxs_dma_channels).
132 #define MXS_DMA_FLAGS_IDLE 0
133 #define MXS_DMA_FLAGS_BUSY (1 << 0)
134 #define MXS_DMA_FLAGS_FREE 0
135 #define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
136 #define MXS_DMA_FLAGS_VALID (1 << 31)
138 struct mxs_dma_chan {
141 struct mxs_dma_device *dma;
143 unsigned int active_num;
144 unsigned int pending_num;
145 struct list_head active;
146 struct list_head done;
149 struct mxs_dma_desc *mxs_dma_desc_alloc(void);
150 void mxs_dma_desc_free(struct mxs_dma_desc *);
151 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
153 int mxs_dma_go(int chan);
154 void mxs_dma_init(void);
155 int mxs_dma_init_channel(int chan);
156 int mxs_dma_release(int chan);
158 void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
160 #endif /* __DMA_H__ */