arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPIDR     5
  12
  13 #define CPUID_EXT_PFR0  "c1, 0"
  14 #define CPUID_EXT_PFR1  "c1, 1"
  15 #define CPUID_EXT_DFR0  "c1, 2"
  16 #define CPUID_EXT_AFR0  "c1, 3"
  17 #define CPUID_EXT_MMFR0 "c1, 4"
  18 #define CPUID_EXT_MMFR1 "c1, 5"
  19 #define CPUID_EXT_MMFR2 "c1, 6"
  20 #define CPUID_EXT_MMFR3 "c1, 7"
  21 #define CPUID_EXT_ISAR0 "c2, 0"
  22 #define CPUID_EXT_ISAR1 "c2, 1"
  23 #define CPUID_EXT_ISAR2 "c2, 2"
  24 #define CPUID_EXT_ISAR3 "c2, 3"
  25 #define CPUID_EXT_ISAR4 "c2, 4"
  26 #define CPUID_EXT_ISAR5 "c2, 5"
  27
  28 #define MPIDR_SMP_BITMASK (0x3 << 30)
  29 #define MPIDR_SMP_VALUE (0x2 << 30)
  30
  31 #define MPIDR_MT_BITMASK (0x1 << 24)
  32
  33 #define MPIDR_HWID_BITMASK 0xFFFFFF
  34
  35 #define MPIDR_LEVEL_BITS 8
  36 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  37
  38 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  39         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  40
  41 extern unsigned int processor_id;
  42
  43 #ifdef CONFIG_CPU_CP15
  44 #define read_cpuid(reg)                                                 \
  45         ({                                                              \
  46                 unsigned int __val;                                     \
  47                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  48                     : "=r" (__val)                                      \
  49                     :                                                   \
  50                     : "cc");                                            \
  51                 __val;                                                  \
  52         })
  53 #define read_cpuid_ext(ext_reg)                                         \
  54         ({                                                              \
  55                 unsigned int __val;                                     \
  56                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
  57                     : "=r" (__val)                                      \
  58                     :                                                   \
  59                     : "cc");                                            \
  60                 __val;                                                  \
  61         })
  62 #else
  63 #define read_cpuid(reg) (processor_id)
  64 #define read_cpuid_ext(reg) 0
  65 #endif
  66
  67 #define ARM_CPU_IMP_ARM                 0x41
  68 #define ARM_CPU_IMP_INTEL               0x69
  69
  70 #define ARM_CPU_PART_ARM1136            0xB360
  71 #define ARM_CPU_PART_ARM1156            0xB560
  72 #define ARM_CPU_PART_ARM1176            0xB760
  73 #define ARM_CPU_PART_ARM11MPCORE        0xB020
  74 #define ARM_CPU_PART_CORTEX_A8          0xC080
  75 #define ARM_CPU_PART_CORTEX_A9          0xC090
  76 #define ARM_CPU_PART_CORTEX_A5          0xC050
  77 #define ARM_CPU_PART_CORTEX_A15         0xC0F0
  78 #define ARM_CPU_PART_CORTEX_A7          0xC070
  79
  80 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  81 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  82 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  83 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  84
  85 /*
  86  * The CPU ID never changes at run time, so we might as well tell the
  87  * compiler that it's constant.  Use this function to read the CPU ID
  88  * rather than directly reading processor_id or read_cpuid() directly.
  89  */
  90 static inline unsigned int __attribute_const__ read_cpuid_id(void)
  91 {
  92         return read_cpuid(CPUID_ID);
  93 }
  94
  95 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
  96 {
  97         return (read_cpuid_id() & 0xFF000000) >> 24;
  98 }
  99
 100 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 101 {
 102         return read_cpuid_id() & 0xFFF0;
 103 }
 104
 105 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 106 {
 107         return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
 108 }
 109
 110 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 111 {
 112         return read_cpuid(CPUID_CACHETYPE);
 113 }
 114
 115 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 116 {
 117         return read_cpuid(CPUID_TCM);
 118 }
 119
 120 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 121 {
 122         return read_cpuid(CPUID_MPIDR);
 123 }
 124
 125 /*
 126  * Intel's XScale3 core supports some v6 features (supersections, L2)
 127  * but advertises itself as v5 as it does not support the v6 ISA.  For
 128  * this reason, we need a way to explicitly test for this type of CPU.
 129  */
 130 #ifndef CONFIG_CPU_XSC3
 131 #define cpu_is_xsc3()   0
 132 #else
 133 static inline int cpu_is_xsc3(void)
 134 {
 135         unsigned int id;
 136         id = read_cpuid_id() & 0xffffe000;
 137         /* It covers both Intel ID and Marvell ID */
 138         if ((id == 0x69056000) || (id == 0x56056000))
 139                 return 1;
 140
 141         return 0;
 142 }
 143 #endif
 144
 145 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
 146 #define cpu_is_xscale() 0
 147 #else
 148 #define cpu_is_xscale() 1
 149 #endif
 150
 151 #endif