1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11 #include <asm/system.h>
16 * Invalidate L2 Cache using co-proc instruction
18 #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
19 void invalidate_l2_cache(void);
21 static inline void invalidate_l2_cache(void)
25 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
26 : : "r" (val) : "cc");
31 int check_cache_range(unsigned long start, unsigned long stop);
33 void l2_cache_enable(void);
34 void l2_cache_disable(void);
35 void set_section_dcache(int section, enum dcache_option option);
37 void arm_init_before_mmu(void);
38 void cpu_cache_initialization(void);
39 void dram_bank_mmu_setup(int bank);
44 * The value of the largest data cache relevant to DMA operations shall be set
45 * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger
46 * value than found in the L1 cache but this is OK to use in terms of
49 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
52 * arm_reserve_mmu() - Reserve memory for MMU TLB table
54 * Default implementation for reserving memory for MMU TLB table. It is used
55 * during generic board init sequence in common/board_f.c. Weakly defined, so
56 * that machines can override it if needed.
60 int arm_reserve_mmu(void);
62 #endif /* _ASM_CACHE_H */