3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/system.h>
17 * Invalidate L2 Cache using co-proc instruction
19 static inline void invalidate_l2_cache(void)
23 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
24 : : "r" (val) : "cc");
28 void l2_cache_enable(void);
29 void l2_cache_disable(void);
30 void set_section_dcache(int section, enum dcache_option option);
32 void dram_bank_mmu_setup(int bank);
37 * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
38 * use that value for aligning DMA buffers unless the board config has specified
39 * an alternate cache line size.
41 #ifdef CONFIG_SYS_CACHELINE_SIZE
42 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
44 #define ARCH_DMA_MINALIGN 64
47 #endif /* _ASM_CACHE_H */