1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
7 #ifndef _ASM_ARMV7_MPU_H
8 #define _ASM_ARMV7_MPU_H
11 #include <linux/bitops.h>
21 #else /* CONFIG_CPU_V7R */
28 #endif /* CONFIG_CPU_V7R */
30 #define CACHEABLE BIT(C_SHIFT)
31 #define BUFFERABLE BIT(B_SHIFT)
32 #define SHAREABLE BIT(S_SHIFT)
33 #define REGION_SIZE_SHIFT 1
34 #define ENABLE_REGION BIT(0)
35 #define DISABLE_REGION 0
60 SHARED_WRITE_BUFFERED,
85 struct mpu_region_config {
87 enum region_number region_no;
94 void disable_mpu(void);
95 void enable_mpu(void);
96 int mpu_enabled(void);
97 void mpu_config(struct mpu_region_config *reg_config);
98 void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns);
100 static inline u32 get_attr_encoding(u32 mr_attr)
108 case SHARED_WRITE_BUFFERED:
111 case O_I_WT_NO_WR_ALLOC:
114 case O_I_WB_NO_WR_ALLOC:
115 attr = CACHEABLE | BUFFERABLE;
117 case O_I_NON_CACHEABLE:
118 attr = 1 << TEX_SHIFT;
120 case O_I_WB_RD_WR_ALLOC:
121 attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
123 case DEVICE_NON_SHARED:
124 attr = (2 << TEX_SHIFT) | BUFFERABLE;
127 attr = 0; /* strongly ordered */
134 #endif /* _ASM_ARMV7_MPU_H */