2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
21 #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
25 /* Clock Controller Module (CCM) */
69 /* Analog components control digital interface (ANADIG) */
126 #define CCM_CCR_FIRC_EN (1 << 16)
127 #define CCM_CCR_OSCNT_MASK 0xff
128 #define CCM_CCR_OSCNT(v) ((v) & 0xff)
130 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
131 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
132 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
134 #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
135 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
136 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
138 #define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
139 #define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
140 #define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
141 #define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
142 #define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
143 #define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
144 #define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
145 #define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
147 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
148 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
150 #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
151 #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
152 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
154 #define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
155 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
156 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
157 #define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
158 #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
159 #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
160 #define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
161 #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
162 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
164 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
165 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
166 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
168 #define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
170 #define CCM_CSCDR2_ESDHC1_EN (1 << 29)
171 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
172 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
173 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
175 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
176 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
177 #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
179 #define CCM_REG_CTRL_MASK 0xffffffff
180 #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
181 #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
182 #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
183 #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
184 #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
185 #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
186 #define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
187 #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
188 #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
189 #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
190 #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
191 #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
192 #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
193 #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
194 #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
195 #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
196 #define CCM_CCGR9_FEC0_CTRL_MASK 0x3
197 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
199 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
200 #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
201 #define ANADIG_PLL2_CTRL_DIV_SELECT 1
202 #define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
203 #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
204 #define ANADIG_PLL1_CTRL_DIV_SELECT 1
206 #define FASE_CLK_FREQ 24000000
207 #define SLOW_CLK_FREQ 32000
208 #define PLL1_PFD1_FREQ 500000000
209 #define PLL1_PFD2_FREQ 452000000
210 #define PLL1_PFD3_FREQ 396000000
211 #define PLL1_PFD4_FREQ 528000000
212 #define PLL1_MAIN_FREQ 528000000
213 #define PLL2_PFD1_FREQ 500000000
214 #define PLL2_PFD2_FREQ 396000000
215 #define PLL2_PFD3_FREQ 339000000
216 #define PLL2_PFD4_FREQ 413000000
217 #define PLL2_MAIN_FREQ 528000000
218 #define PLL3_MAIN_FREQ 480000000
219 #define PLL3_PFD3_FREQ 298000000
220 #define PLL5_MAIN_FREQ 500000000
222 #define ENET_EXTERNAL_CLK 50000000
223 #define AUDIO_EXTERNAL_CLK 24576000
225 #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */