1 /******************************************************************************
2 ** File Name: sc8810_reg_global.h *
3 ** Author: Daniel.Ding *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 11/13/2005 Daniel.Ding Create. *
13 ** 05/05/2010 Mingwei.Zhang Modified for SC8800G *
14 ******************************************************************************/
15 #ifndef _SC8810_REG_GLOBAL_H_
16 #define _SC8810_REG_GLOBAL_H_
17 /*----------------------------------------------------------------------------*
19 **-------------------------------------------------------------------------- */
21 /**---------------------------------------------------------------------------*
23 **---------------------------------------------------------------------------*/
28 /**----------------------------------------------------------------------------*
30 **----------------------------------------------------------------------------*/
33 /*----------Global Registers----------*/
34 //GREG_BASE 0x8B000000
35 #define GR_GEN0 (GREG_BASE + 0x0008)
36 #define GR_PCTL (GREG_BASE + 0x000C)
37 #define GR_IRQ (GREG_BASE + 0x0010)
38 #define GR_ICLR (GREG_BASE + 0x0014)
39 #define GR_GEN1 (GREG_BASE + 0x0018)
40 #define GR_GEN3 (GREG_BASE + 0x001C)
41 //#define GR_HWRST (GREG_BASE + 0x0020)
42 #define BOOT_FLAG (GREG_BASE + 0x0020) //It's called GR_HWRST in other chip define
43 #define GR_MPLL_MN (GREG_BASE + 0x0024)
44 #define GR_PIN_CTL (GREG_BASE + 0x0028)
45 #define GR_GEN2 (GREG_BASE + 0x002C)
46 #define GR_ARM_BOOT_ADDR (GREG_BASE + 0x0030)
47 #define GR_STC_STATE (GREG_BASE + 0x0034)
49 #define GR_BUSCLK (GREG_BASE + 0x0044) ////GR_BUSCLK_ALM
50 #define GR_ARCH_CTL (GREG_BASE + 0x0048)
51 #define GR_SOFT_RST (GREG_BASE + 0x004C)
53 #define GR_NFC_MEM_DLY (GREG_BASE + 0x0058)
54 #define GR_CLK_DLY (GREG_BASE + 0x005C)
55 #define GR_GEN4 (GREG_BASE + 0x0060)
57 #define GR_POWCTL0 (GREG_BASE + 0x0068)
58 #define GR_POWCTL1 (GREG_BASE + 0x006C)
59 #define GR_PLL_SCR (GREG_BASE + 0x0070)
60 #define GR_CLK_EN (GREG_BASE + 0x0074)
62 #define GR_CLK_GEN5 (GREG_BASE + 0x007C)
64 #define GR_SWRST GR_SOFT_RST ////mingweiflag GR_SOFT_RST or GR_SWRST?
65 #define GR_BUSCLK_ALM GR_BUSCLK
66 #define LDO_USB_PD BIT_9
71 #define GEN0_TIMER_EN BIT_2
72 #define GEN0_SIM0_EN BIT_3
73 #define GEN0_I2C_EN BIT_4
74 #define GEN0_GPIO_EN BIT_5
75 #define GEN0_ADI_EN BIT_6
76 #define GEN0_EFUSE_EN BIT_7
77 #define GEN0_KPD_EN BIT_8
79 #define GEN0_MCU_DSP_RST BIT_10
80 #define GEN0_MCU_SOFT_RST BIT_11
81 #define GEN0_I2S_EN BIT_12
82 #define GEN0_PIN_EN BIT_13
83 #define GEN0_CCIR_MCLK_EN BIT_14
84 #define GEN0_EPT_EN BIT_15
85 #define GEN0_SIM1_EN BIT_16
86 #define GEN0_SPI_EN BIT_17
88 #define GEN0_SYST_EN BIT_19
89 #define GEN0_UART0_EN BIT_20
90 #define GEN0_UART1_EN BIT_21
91 #define GEN0_UART2_EN BIT_22
92 #define GEN0_VB_EN BIT_23
93 #define GEN0_GPIO_RTC_EN BIT_24
95 #define GEN0_KPD_RTC_EN BIT_26
96 #define GEN0_SYST_RTC_EN BIT_27
97 #define GEN0_TMR_RTC_EN BIT_28
101 the GEN1 register bit
103 #define GEN1_MPLL_MN_EN BIT_9
104 #define GEN1_CLK_AUX0_EN BIT_10
105 #define GEN1_CLK_AUX1_EN BIT_11
107 #define GEN1_RTC_ARCH_EN BIT_18
110 #define MISC0_UART1_MUX_SEL BIT_8
113 the APB Soft Reset register bit
115 #define SWRST_I2C_RST BIT_0
116 #define SWRST_KPD_RST BIT_1
118 #define SWRST_SIM0_RST BIT_5
119 #define SWRST_SIM1_RST BIT_6
121 #define SWRST_TIMER_RST BIT_8
123 #define SWRST_EPT_RST BIT_10
124 #define SWRST_UART0_RST BIT_11
125 #define SWRST_UART1_RST BIT_12
126 #define SWRST_UART2_RST BIT_13
127 #define SWRST_SPI_RST BIT_14
129 #define SWRST_IIS_RST BIT_16
131 #define SWRST_SYST_RST BIT_19
132 #define SWRST_PINREG_RST BIT_20
133 #define SWRST_GPIO_RST BIT_21
134 #define ADI_SOFT_RST BIT_22
135 #define SWRST_VBC_RST BIT_23
136 #define SWRST_PWM0_RST BIT_24
137 #define SWRST_PWM1_RST BIT_25
138 #define SWRST_PWM2_RST BIT_26
139 #define SWRST_PWM3_RST BIT_27
140 #define SWRST_EFUSE_RST BIT_28
144 the ARM VB CTRL register bit
146 #define ARM_VB_IIS_SEL BIT_0
147 #define ARM_VB_MCLKON BIT_1
148 #define ARM_VB_DA0ON BIT_2
149 #define ARM_VB_DA1ON BIT_3
150 #define ARM_VB_AD0ON BIT_4
151 #define ARM_VB_AD1ON BIT_5
152 #define ARM_VB_ANAON BIT_6
153 #define ARM_VB_ACC BIT_7
155 #define ARM_VB_ADCON ARM_VB_AD0ON
159 the Interrupt control register bit
161 #define IRQ_MCU_IRQ0 BIT_0
162 #define IRQ_MCU_FRQ0 BIT_1
163 #define IRQ_MCU_IRQ1 BIT_2
164 #define IRQ_MCU_FRQ1 BIT_3
166 #define IRQ_VBCAD_IRQ BIT_5
167 #define IRQ_VBCDA_IRQ BIT_6
169 #define IRQ_RFT_INT BIT_12
172 the Interrupt clear register bit
174 #define ICLR_DSP_IRQ0_CLR BIT_0
175 #define ICLR_DSP_FRQ0_CLR BIT_1
176 #define ICLR_DSP_IRQ1_CLR BIT_2
177 #define ICLR_DSP_FIQ1_CLR BIT_3
179 #define ICLR_VBCAD_IRQ_CLR BIT_5
180 #define ICLR_VBCDA_IRQ_CLR BIT_6
182 #define ICLR_RFT_INT_CLR BIT_12
186 the Clock enable register bit
189 #define CLK_PWM0_EN BIT_21
190 #define CLK_PWM1_EN BIT_22
191 #define CLK_PWM2_EN BIT_23
192 #define CLK_PWM3_EN BIT_24
193 #define CLK_PWM0_SEL BIT_25
194 #define CLK_PWM1_SEL BIT_26
195 #define CLK_PWM2_SEL BIT_27
196 #define CLK_PWM3_SEL BIT_28
199 #define POWCTL1_CONFIG 0x7FFFF91E // isolation number 1ms:30cycles
202 /**----------------------------------------------------------------------------*
204 **----------------------------------------------------------------------------*/
205 #ifdef CHIP_ENDIAN_LITTLE
206 typedef union _gr_anatst_ctl_tag
208 struct _gr_anatst_ctl_map
210 volatile unsigned int start_en1u :1;
211 volatile unsigned int start_en1u_rst :1;
212 volatile unsigned int start_en2u :1;
213 volatile unsigned int start_en2u_rst :1;
214 volatile unsigned int start_en3u :1;
215 volatile unsigned int start_en3u_rst :1;
216 volatile unsigned int start_en6u :1;
217 volatile unsigned int start_en6u_rst :1;
218 volatile unsigned int Ldo_bpnf :1;
219 volatile unsigned int Ldo_bpnf_rst :1;
220 volatile unsigned int Ldo_bprf2 :1;
221 volatile unsigned int Ldo_bprf2_rst :1;
222 volatile unsigned int Ldo_bpusb :2; //USB
223 volatile unsigned int recharge :1;
224 volatile unsigned int standby :1;
225 volatile unsigned int Slp_usb_en :1;
226 volatile unsigned int Reserved :1;
227 volatile unsigned int Ldo_ldo3_b0 :1;
228 volatile unsigned int Ldo_ldo3_b0_rst :1;
229 volatile unsigned int Ldo_ldo3_b1 :1;
230 volatile unsigned int Ldo_ldo3_b1_rst :1;
231 volatile unsigned int Ldo_ldo2_b0 :1;
232 volatile unsigned int Ldo_ldo2_b0_rst :1;
233 volatile unsigned int Adapter_en :2;
234 volatile unsigned int Usb_500ma_en :2;
235 volatile unsigned int Charger_ctl :4;
237 volatile unsigned int dwValue ;
241 typedef union _gr_nfc_mem_dly_tag
243 struct _gr_nfc_mem_dly_map
245 volatile unsigned int nefc_cen_dly_sel :3;
246 volatile unsigned int nfc_cle_dly_sel :3;
247 volatile unsigned int nfc_ale_dly_sel :3;
248 volatile unsigned int nfc_wen_dly_sel :3;
249 volatile unsigned int nfc_ren_dly_sel :3;
250 volatile unsigned int nfc_wpn_dly_sel :3;
251 volatile unsigned int nfc_data0_dly_sel :3;
252 volatile unsigned int nfc_data8_dly_sel :3;
253 volatile unsigned int reserved :8;//Reserved
255 volatile unsigned int dwValue;
258 typedef union _gr_gen1_reg_tag
260 struct _gr_gen1_reg_map
262 volatile unsigned int vlk_aux0_div :7;
263 volatile unsigned int reserved_2 :1;
264 volatile unsigned int gea_eb2 :1;
265 volatile unsigned int m_pllmn_we :1;
266 volatile unsigned int clk_aux0_en :1;
267 volatile unsigned int clk_aux1_en :1;
268 volatile unsigned int testmodep_mcu2 :1;
269 volatile unsigned int syst_en3 :1;
270 volatile unsigned int serclk_eb3 :1;
271 volatile unsigned int clk_26mhz_en :1;
272 volatile unsigned int clk_aux0_sel :2;
273 volatile unsigned int clk_aux1_sel :2;
274 volatile unsigned int v_pllmn_we :1;
275 volatile unsigned int a_pllmn_we :1;
276 volatile unsigned int serclk_eb0 :1;
277 volatile unsigned int serclk_eb1 :1;
278 volatile unsigned int serclk_eb2 :1;
279 volatile unsigned int arm_boot_md0 :1;
280 volatile unsigned int arm_boot_md1 :1;
281 volatile unsigned int arm_boot_md2 :1;
282 volatile unsigned int arm_boot_md3 :1;
283 volatile unsigned int arm_boot_md4 :1;
284 volatile unsigned int arm_boot_md5 :1;
285 volatile unsigned int reserved_1 :1;//Reserved
287 volatile unsigned int dwValue;
290 typedef union _gr_glb_gen4_reg_tag
292 struct _gr_glb_gen4_reg_map
294 volatile unsigned int clk_lcdc_div :7;
295 volatile unsigned int reserved_2 :1;
296 volatile unsigned int clk_pll_source_sel :8;
297 volatile unsigned int reserved_1 :16;
299 volatile unsigned int dwValue;
302 typedef union _gr_anatst_ctl_tag
304 struct _gr_anatst_ctl_map
306 volatile unsigned int Charger_ctl :4;
307 volatile unsigned int Usb_500ma_en :2;
308 volatile unsigned int Adapter_en :2;
309 volatile unsigned int Ldo_ldo2_b0_rst :1;
310 volatile unsigned int Ldo_ldo2_b0 :1;
311 volatile unsigned int Ldo_ldo3_b1_rst :1;
312 volatile unsigned int Ldo_ldo3_b1 :1;
313 volatile unsigned int Ldo_ldo3_b0_rst :1;
314 volatile unsigned int Ldo_ldo3_b0 :1;
315 volatile unsigned int Reserved :1;
316 volatile unsigned int Slp_usb_en :1;
317 volatile unsigned int standby :1;
318 volatile unsigned int recharge :1;
319 volatile unsigned int Ldo_bpusb :2; //USB
320 volatile unsigned int Ldo_bprf2_rst :1;
321 volatile unsigned int Ldo_bprf2 :1;
322 volatile unsigned int Ldo_bpnf_rst :1;
323 volatile unsigned int Ldo_bpnf :1;
324 volatile unsigned int start_en6u_rst :1;
325 volatile unsigned int start_en6u :1;
326 volatile unsigned int start_en3u_rst :1;
327 volatile unsigned int start_en3u :1;
328 volatile unsigned int start_en2u_rst :1;
329 volatile unsigned int start_en2u :1;
330 volatile unsigned int start_en1u_rst :1;
331 volatile unsigned int start_en1u :1;
333 volatile unsigned int dwValue ;
337 typedef union _gr_nfc_mem_dly_tag
339 struct _gr_nfc_mem_dly_map
341 volatile unsigned int reserved :8;//Reserved
342 volatile unsigned int nfc_data8_dly_sel :3;
343 volatile unsigned int nfc_data0_dly_sel :3;
344 volatile unsigned int nfc_wpn_dly_sel :3;
345 volatile unsigned int nfc_ren_dly_sel :3;
346 volatile unsigned int nfc_wen_dly_sel :3;
347 volatile unsigned int nfc_ale_dly_sel :3;
348 volatile unsigned int nfc_cle_dly_sel :3;
349 volatile unsigned int nefc_cen_dly_sel :3;
351 volatile unsigned int dwValue;
354 typedef union _gr_gen1_reg_tag
356 struct _gr_gen1_reg_map
358 volatile unsigned int reserved_1 :1;//Reserved
359 volatile unsigned int arm_boot_md5 :1;
360 volatile unsigned int arm_boot_md4 :1;
361 volatile unsigned int arm_boot_md3 :1;
362 volatile unsigned int arm_boot_md2 :1;
363 volatile unsigned int arm_boot_md1 :1;
364 volatile unsigned int arm_boot_md0 :1;
365 volatile unsigned int serclk_eb2 :1;
366 volatile unsigned int serclk_eb1 :1;
367 volatile unsigned int serclk_eb0 :1;
368 volatile unsigned int a_pllmn_we :1;
369 volatile unsigned int v_pllmn_we :1;
370 volatile unsigned int clk_aux1_sel :2;
371 volatile unsigned int clk_aux0_sel :2;
372 volatile unsigned int clk_26mhz_en :1;
373 volatile unsigned int serclk_eb3 :1;
374 volatile unsigned int syst_en3 :1;
375 volatile unsigned int testmodep_mcu2 :1;
376 volatile unsigned int clk_aux1_en :1;
377 volatile unsigned int clk_aux0_en :1;
378 volatile unsigned int m_pllmn_we :1;
379 volatile unsigned int gea_eb2 :1;
380 volatile unsigned int reserved_2 :1;
381 volatile unsigned int vlk_aux0_div :7;
383 volatile unsigned int dwValue;
386 typedef union _gr_glb_gen4_reg_tag
388 struct _gr_glb_gen4_reg_map
390 volatile unsigned int reserved_1 :16;
391 volatile unsigned int clk_pll_source_sel :8;
392 volatile unsigned int reserved_2 :1;
393 volatile unsigned int clk_lcdc_div :7;
395 volatile unsigned int dwValue;
398 /**----------------------------------------------------------------------------*
399 ** Local Function Prototype **
400 **----------------------------------------------------------------------------*/
402 /**----------------------------------------------------------------------------*
403 ** Function Prototype **
404 **----------------------------------------------------------------------------*/
407 /**----------------------------------------------------------------------------*
409 **----------------------------------------------------------------------------*/
413 /**---------------------------------------------------------------------------*/
414 #endif //_SC8810_REG_GLOBAL_H_