2 * arch/arm/mach-sc8800s/include/mach/regs_ahb.h
4 * Chip AHB registers Definitions
6 * Copyright (C) 2010 Spreadtrum International Ltd.
8 * 2010-05-25: yingchun li <yingchun.li@spreadtrum.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef _SC8800H_REG_AHB_H_
17 #define _SC8800H_REG_AHB_H_
19 #include <asm/arch/bits.h>
21 #define AHB_REG_BASE 0x20900200
22 #define CHIP_TYPE 0x209003FC
24 #define AHB_CTL0 (AHB_REG_BASE + 0x00)
25 #define AHB_CTL1 (AHB_REG_BASE + 0x04)
26 #define AHB_CTL2 (AHB_REG_BASE + 0x08)
27 #define AHB_CTL3 (AHB_REG_BASE + 0x0C)
28 #define AHB_SOFT_RST (AHB_REG_BASE + 0x10)
29 #define AHB_PAUSE (AHB_REG_BASE + 0x14)
30 #define AHB_REMAP (AHB_REG_BASE + 0x18)
31 #define AHB_ARM_CLK (AHB_REG_BASE + 0x24)
32 #define AHB_SDIO_CTL (AHB_REG_BASE + 0x28)
33 #define AHB_CTL4 (AHB_REG_BASE + 0x2C)
34 #define AHB_ENDIAN_SEL (AHB_REG_BASE + 0x30)
35 #define AHB_STS (AHB_REG_BASE + 0x34)
36 #define DSP_BOOT_EN (AHB_REG_BASE + 0x84)
37 #define DSP_BOOT_VEC (AHB_REG_BASE + 0x88)
38 #define DSP_RST (AHB_REG_BASE + 0x8C)
39 #define AHB_ENDIAN_EN (AHB_REG_BASE + 0x90)
40 #define USB_PHY_CTRL (AHB_REG_BASE + 0xA0)
41 #define USB_SPR_REG (AHB_REG_BASE + 0xC0)
43 #define CHIP_ID (AHB_REG_BASE + 0x1FC)
45 #define AHB_DSP_BOOT_EN (AHB_REG_BASE + 0x84)
46 #define AHB_DSP_BOOT_VECTOR (AHB_REG_BASE + 0x88)
47 #define AHB_DSP_RESET (AHB_REG_BASE + 0x8C)
48 #define AHB_BIGEND_PROT_REG (AHB_REG_BASE + 0x90)
50 #define AHB_CTL0_DCAM_EN BIT_1
51 #define AHB_CTL0_CCIR_EN BIT_2
52 #define AHB_CTL0_LCDC_EN BIT_3
53 #define AHB_CTL0_SDIO_EN BIT_4
54 #define AHB_CTL0_USBD_EN BIT_5
55 #define AHB_CTL0_DMA_EN BIT_6
56 #define AHB_CTL0_BM0_EN (BIT_7)
57 #define AHB_CTL0_NFC_EN BIT_8
58 #define AHB_CTL0_BM1_EN (BIT_11)
59 #define AHB_CTL0_VSP_EN BIT_13
60 #define AHB_CTL0_ROT_EN BIT_14
61 #define AHB_CTL0_DRM_EN BIT_18
62 #define AHB_CTL0_AHB_ARCH_EB BIT_15
63 #define AHB_CTL0_EMC_EN BIT_28
65 #define AHB_BIGENDIAN_DMA BIT_0
66 #define AHB_BIGENDIAN_NFC BIT_1
67 #define AHB_BIGENDIAN_LCDC BIT_2
68 #define AHB_BIGENDIAN_SDIO BIT_3
69 #define AHB_BIGENDIAN_DCAM BIT_4
70 #define AHB_BIGENDIAN_VSP BIT_5
71 #define AHB_BIGENDIAN_ROT BIT_6
72 #define AHB_BIGENDIAN_BM0 BIT_7
73 #define AHB_BIGENDIAN_BM1 BIT_8
74 #define AHB_BIGENDIAN_SHARM BIT_9
76 #define AHB_ENDIAN_OPEN 0xC3D4
77 // Bit define AHB_CTRL1
78 #define AHB_CTRL1_EMC_AUTO_GATE_EN BIT_8
79 #define AHB_CTRL1_EMC_CH_AUTO_GATE_EN BIT_9
80 #define AHB_CTRL1_ARM_AUTO_GATE_EN BIT_11
81 #define AHB_CTRL1_AHB_AUTO_GATE_EN BIT_12
82 #define AHB_CTRL1_MCU_AUTO_GATE_EN BIT_13
83 #define AHB_CTRL1_MSTMTX_AUTO_GATE_EN BIT_14
84 #define AHB_CTRL1_ARMMTX_AUTO_GATE_EN BIT_15
85 #define AHB_CTRL1_ARM_DAHB_SLEEP_EN BIT_16
88 #define USB_DM_PULLUP_BIT BIT_19
89 #define USB_DP_PULLDOWN_BIT BIT_20
90 #define USB_DM_PULLDOWN_BIT BIT_21