1 /******************************************************************************
2 ** File Name: analog_reg_v3.h *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 03/03/2010 Tim.Luo Create. *
13 ** 05/07/2010 Mingwei.zhang Modify it for SC8800G. *
14 ******************************************************************************/
16 #ifndef _ANALOG_REG_V3_H_
17 #define _ANALOG_REG_V3_H_
20 #include "sc8810_reg_base.h"
21 /*----------------------------------------------------------------------------*
23 **-------------------------------------------------------------------------- */
25 /**---------------------------------------------------------------------------*
27 **---------------------------------------------------------------------------*/
32 /**----------------------------------------------------------------------------*
34 **----------------------------------------------------------------------------*/
36 //Analog die register define
38 //#define ANA_REG_BASE 0x82000600
39 #define ANA_APB_CLK_EN (ANA_REG_BASE + 0x00)
40 #define ANA_APB_ARM_RST (ANA_REG_BASE + 0x04)
41 #define ANA_LDO_PD_SET (ANA_REG_BASE + 0x08)
42 #define ANA_LDO_PD_RST (ANA_REG_BASE + 0x0C)
43 #define ANA_LDO_PD_CTL0 (ANA_REG_BASE + 0x10)
44 #define ANA_LDO_PD_CTL1 (ANA_REG_BASE + 0x14)
45 #define ANA_LDO_VCTL0 (ANA_REG_BASE + 0x18)
46 #define ANA_LDO_VCTL1 (ANA_REG_BASE + 0x1C)
47 #define ANA_LDO_VCTL2 (ANA_REG_BASE + 0x20)
48 #define ANA_LDO_VCTL3 (ANA_REG_BASE + 0x24)
49 #define ANA_LDO_VCTL4 (ANA_REG_BASE + 0x28)
50 #define ANA_LDO_SLP_CTL0 (ANA_REG_BASE + 0x2C)
51 #define ANA_LDO_SLP_CTL1 (ANA_REG_BASE + 0x30)
52 #define ANA_LDO_SLP_CTL2 (ANA_REG_BASE + 0x34)
53 #define ANA_DCDC_CTL (ANA_REG_BASE + 0x38)
54 #define ANA_DCDC_CTL_DS (ANA_REG_BASE + 0x3C)
55 #define ANA_DCDC_CTL_CAL (ANA_REG_BASE + 0x40)
56 #define ANA_DCDCARM_CTL (ANA_REG_BASE + 0x44)
57 #define ANA_DCDCARM_CTL_CAL (ANA_REG_BASE + 0x48)
58 #define ANA_PLL_CTL (ANA_REG_BASE + 0x4C)
59 #define ANA_APLLMN (ANA_REG_BASE + 0x50)
60 #define ANA_APLLWAIT (ANA_REG_BASE + 0x54)
61 #define ANA_RTC_CTL (ANA_REG_BASE + 0x58)
62 #define ANA_TRF_CTL (ANA_REG_BASE + 0x5C)
63 #define ANA_CHGR_CTL0 (ANA_REG_BASE + 0x60)
64 #define ANA_CHGR_CTL1 (ANA_REG_BASE + 0x64)
65 #define ANA_LED_CTL (ANA_REG_BASE + 0x68)
66 #define ANA_VIBRATOR_CTL0 (ANA_REG_BASE + 0x6C)
67 #define ANA_VIBRATOR_CTL1 (ANA_REG_BASE + 0x70)
68 #define ANA_AUDIO_CTL (ANA_REG_BASE + 0x74)
69 #define ANA_AUDIO_PA_CTL0 (ANA_REG_BASE + 0x78)
70 #define ANA_AUDIO_PA_CTL1 (ANA_REG_BASE + 0x7C)
71 #define ANA_MIXED_CTL (ANA_REG_BASE + 0x80)
72 #define ANA_STATUS (ANA_REG_BASE + 0x84)
73 #define ANA_HWRST_STATUS (ANA_REG_BASE + 0x88)
74 #define ANA_MCU_WR_PROT (ANA_REG_BASE + 0x8C)
75 #define ANA_VIBR_WR_PROT (ANA_REG_BASE + 0x90)
76 #define ANA_INT_GPI_DEBUG (ANA_REG_BASE + 0x94)
77 #define ANA_HWRST_RTC (ANA_REG_BASE + 0x98)
78 #define ANA_IF_SPR_CTRL (ANA_REG_BASE + 0x9C)
79 #define ANA_CHIP_ID_LOW (ANA_REG_BASE + 0xF8)
80 #define ANA_CHIP_ID_HIGH (ANA_REG_BASE + 0xFC)
83 the APB_CLK_EN register bit
86 #define CHGRWDG_EB BIT_15
87 #define CLK_AUXAD_EN BIT_14
88 #define CLK_AUXADC_EN BIT_13
89 #define RTC_TPC_EB BIT_12
90 #define RTC_EIC_EB BIT_11
91 #define RTC_WDG_EB BIT_10
92 #define RTC_RTC_EB BIT_9
93 #define RTC_ARCH_EB BIT_8
94 #define PINREG_EB BIT_7
95 #define AGEN_RTC_EN BIT_1
96 #define AGEN_RTC_RTC_EN BIT_9
104 #define APB_ARCH_EB BIT_0
107 the APB_ARM_RST register bit
109 #define GPIO_SOFT_RST BIT_7
110 #define EIC_SOFT_RST BIT_6
111 #define TPC_SOFT_RST BIT_5
112 #define ADC_SOFT_RST BIT_4
113 #define WDG_SOFT_RST BIT_3
114 #define CHGRWDG_SOFT_RST BIT_2
115 #define VBMC_SOFT_RST BIT_1
116 #define RTC_SOFT_RST BIT_0
118 the LDO_PD_SET register bit
120 #define DCDCAM_PD BIT_9
121 #define LDO_BPVDD25 BIT_8
122 #define LDO_BPVDD18 BIT_7
123 #define LDO_BPVDD28 BIT_6
124 #define LDO_BPAVDDBB BIT_5
125 #define LDO_BPRF1 BIT_4
126 #define LDO_BPRF0 BIT_3
127 #define LDO_BPMEM BIT_2
128 #define DCDC_PD BIT_1
131 #define ANA_LDO_PD_SET_MSK 0x3FF
133 the LDO_PD_RST register bit
135 #define DCDCAM_PD_RST BIT_9
136 #define LDO_BPVDD25_RST BIT_8
137 #define LDO_BPVDD18_RST BIT_7
138 #define LDO_BPVDD28_RST BIT_6
139 #define LDO_BPAVDDBB_RST BIT_5
140 #define LDO_BPRF1_RST BIT_4
141 #define LDO_BPRF0_RST BIT_3
142 #define LDO_BPMEM_RST BIT_2
143 #define DCDC_PD_RST BIT_1
144 #define PDBG_RST BIT_0
146 the LDO_PD_CTL0 register bit
148 #define LDO_BPVB_RST BIT_15
149 #define LDO_BPVB BIT_14
150 #define LDO_BPCAMA_RST BIT_13
151 #define LDO_BPCAMA BIT_12
152 #define LDO_BPCMAD1_RST BIT_11
153 #define LDO_BPCAMD1 BIT_10
154 #define LDO_BPCMAD0_RST BIT_9
155 #define LDO_BPCAMD0 BIT_8
156 #define LDO_BPSIM1_RST BIT_7
157 #define LDO_BPSIM1 BIT_6
158 #define LDO_BPSIM0_RST BIT_5
159 #define LDO_BPSIM0 BIT_4
160 #define LDO_BPSDIO0_RST BIT_3
161 #define LDO_BPSDIO0 BIT_2
162 #define LDO_BPUSBH_RST BIT_1
163 #define LDO_BPUSBH BIT_0
164 #define ANA_LDO_PD_CTL0_MSK 0x5555
167 the LDO_PD_CTL1 register bit
169 #define LDO_BPSIM3_RST BIT_9
170 #define LDO_BPSIM3 BIT_8
171 #define LDO_BPSIM2_RST BIT_7
172 #define LDO_BPSIM2 BIT_6
173 #define LDO_BPWIFI_RST BIT_5
174 #define LDO_BPWIF1 BIT_4
175 #define LDO_BPWIF0_RST BIT_3
176 #define LDO_BPWIF0 BIT_2
177 #define LDO_BPSDIO1_RST BIT_1
178 #define LDO_BPSDIO1 BIT_0
179 #define ANA_LDO_PD_CTL1_MSK 0x155
181 the LDO_SLP_CTL0 register bit
183 #define FSM_LDOSDIO1_BP_EN BIT_15
184 #define FSM_LDOVDD25_BP_EN BIT_13
185 #define FSM_LDOVDD18_BP_EN BIT_12
186 #define FSM_LDOVDD28_BP_EN BIT_11
188 #define FSM_LDOAVDDBB_BP_EN BIT_10
189 #define FSM_LDOSDIO0_BP_EN BIT_9
190 #define FSM_LDOVB_BP_EN BIT_8
191 #define FSM_CAMA_BP_EN BIT_7
192 #define FSM_CAMD1_BP_EN BIT_6
193 #define FSM_CAMD0_BP_EN BIT_5
194 #define FSM_USBH_BP_EN BIT_4
195 #define FSM_SIM1_BP_EN BIT_3
196 #define FSM_SIM0_BP_EN BIT_2
197 #define FSM_RF1_BP_EN BIT_1
198 #define FSM_RF0_BP_EN BIT_0
201 the LDO_SLP_CTL1 register bit
203 #define FSM_SLPPD_EN BIT_15
204 #define FSM_DCDCARM_BP_EN BIT_4
205 #define FSM_SIM3_BP_EN BIT_3
206 #define FSM_SIM2_BP_EN BIT_2
207 #define FSM_WF1_BP_EN BIT_1
208 #define FSM_WF0_BP_EN BIT_0
210 the DCDC_CTL register bit
212 #define DCDC_RESERVE_RST BIT_13
213 #define DCDC_RESERVE BIT_12
214 #define DCDC_DEDTDELAY_RST BIT_11
215 #define DCDC_DEDTDELAY BIT_10
216 #define DCDC_DEDTDEN_RST BIT_9
217 #define DCDC_DEDTDEN BIT_8
220 #define CHGR_ADAPTER_EN BIT_0
221 #define CHGR_ADAPTER_EN_RST BIT_1
222 #define CHGR_USB_500MA_EN BIT_2
223 #define CHGR_USB_500MA_EN_RST BIT_3
225 #define CHGR_USB_CHG_SHIFT 4
226 #define CHGR_USB_CHG_MSK (3 << CHGR_USB_CHG_SHIFT)
227 #define CHGR_ADAPTER_CHG_SHIFT 6
228 #define CHGR_ADAPTER_CHG_MSK (3 << CHGR_ADAPTER_CHG_SHIFT)
229 #define CHGR_PD_BIT BIT_8
230 #define PA_LDO_EN_RST BIT_9
231 #define CHGR_RECHG_BIT BIT_12
232 #define CHGR_ADATPER_EN_BIT BIT_0
233 #define CHGR_ADATPER_EN_RST_BIT BIT_1
234 #define CHGR_USB_500MA_EN_BIT BIT_2
235 #define CHGR_USB_500MA_EN_RST_BIT BIT_3
236 #define CHAR_ADAPTER_MODE_MSK (BIT_0|BIT_1|BIT_2|BIT_3)
239 #define CHAR_SW_POINT_SHIFT 0
240 #define CHAR_SW_POINT_MSK (0x1F << CHAR_SW_POINT_SHIFT)
243 the VIBRATOR_CTL0 register bit
245 #define VIBR_STABLE_V_SHIFT 12
246 #define VIBR_STABLE_V_MSK (0x0F << VIBR_STABLE_V_SHIFT)
247 #define VIBR_INIT_V_SHIFT 8
248 #define VIBR_INIT_V_MSK (0x0F << VIBR_INIT_V_SHIFT)
249 #define VIBR_V_BP_SHIFT 4
250 #define VIBR_V_BP_MSK (0x0F << VIBR_V_BP_SHIFT)
251 #define VIBR_PD_RST BIT_3
252 #define VIBR_PD_SET BIT_2
253 #define VIBR_BP_EN BIT_1
254 #define VIBR_RTC_EN BIT_0
256 the AUDIO_CTL register bit
258 #define VB_ARM_SOFT_RST BIT_15
259 #define HEADDETECT_PD BIT_7
260 #define LININRE_EN BIT_3
261 #define VBMCLK_SOURCE_SEL BIT_2
262 #define VBMCLK_ARM_ACC BIT_1
263 #define VBMCLK_ARM_EN BIT_0
265 the AUDIO_PA_CTL0 register bit
267 #define PA_OCP_I BIT_12
268 #define PA_OTP_PD BIT_11
269 #define PA_VCM_EN BIT_3
270 #define PA_STOP_EN BIT_2
271 #define PA_EN_RST BIT_5
274 the AUDIO_PA_CTL1 register bit
276 #define PA_ABOCP_PD BIT_15
277 #define PA_DOCP_PD BIT_14
278 #define PA_DEMI_EN BIT_11
279 #define PA_D_EN BIT_10
280 #define PA_LDO_EN_RST BIT_9
281 #define PA_LDO_EN BIT_8
282 #define PA_LDOOCP_PD BIT_7
283 #define PA_SWOCP_PD BIT_2
284 #define PA_SW_EN_RST BIT_1
285 #define PA_SW_EN BIT_0
287 the ANA_MIXED_CTRL register bit
289 #define PTEST_PD_SET BIT_15
290 #define VIBR_PWR_ERR_CLR BIT_7
291 #define CLKBT_EN BIT_6
292 //#define CLK26M_REGS0
293 #define UVH0_EN_RST BIT_3
294 #define UVH0_EN BIT_2
295 #define OTP_EN_RST BIT_1
298 the ANA_STATUS register bit
300 #define VIBR_PWR_ERR BIT_15
301 #define BONDOPT2 BIT_10
302 #define VIBR_PD BIT_9
303 #define WHTLED_PD BIT_8
304 #define CHGR_ON BIT_3
305 #define CHGR_STDBY BIT_2
306 #define BONDOPT1 BIT_1
307 #define BONDOPT0 BIT_0
309 the IF_SPR_CTL register bit
311 #define IF_SPR_IN BIT_2
312 #define IF_SPR_OE BIT_1
313 #define IF_SPR_OUT BIT_0
316 #define HWRST_STATUS_POWERON_MASK (0xf0)
317 #define HWRST_STATUS_RECOVERY (0x20)
318 #define HWRST_STATUS_FASTBOOT (0X30)
319 #define HWRST_STATUS_NORMAL (0X40)
320 #define HWRST_STATUS_ALARM (0X50)
321 #define HWRST_STATUS_SLEEP (0X60)
323 //ryan:add for poweroff debug.
325 #define ANA_LDO_PD_SET_MSK 0x3FF
327 #define ANA_LDO_PD_CTL_MSK 0x5555
329 #define ANA_LDO_PD_RST_MSK 0x0000
330 /**----------------------------------------------------------------------------*
332 **----------------------------------------------------------------------------*/
334 /**----------------------------------------------------------------------------*
335 ** Local Function Prototype **
336 **----------------------------------------------------------------------------*/
338 /**----------------------------------------------------------------------------*
339 ** Function Prototype **
340 **----------------------------------------------------------------------------*/
343 /**----------------------------------------------------------------------------*
345 **----------------------------------------------------------------------------*/
349 /**---------------------------------------------------------------------------*/
351 #endif //_ANALOG_REG_V3_H_