2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define NV_PA_SDRAM_BASE 0x00000000
28 #define NV_PA_ARM_PERIPHBASE 0x50040000
29 #define NV_PA_PG_UP_BASE 0x60000000
30 #define NV_PA_TMRUS_BASE 0x60005010
31 #define NV_PA_CLK_RST_BASE 0x60006000
32 #define NV_PA_FLOW_BASE 0x60007000
33 #define NV_PA_GPIO_BASE 0x6000D000
34 #define NV_PA_EVP_BASE 0x6000F000
35 #define NV_PA_APB_MISC_BASE 0x70000000
36 #define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
37 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
38 #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
39 #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
40 #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
41 #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
42 #define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
43 #define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
44 #define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
45 #define NV_PA_CSITE_BASE 0x70040000
46 #define TEGRA_USB1_BASE 0xC5000000
47 #define TEGRA_USB3_BASE 0xC5008000
48 #define TEGRA_USB_ADDR_MASK 0xFFFFC000
50 #define TEGRA20_SDRC_CS0 NV_PA_SDRAM_BASE
51 #define LOW_LEVEL_SRAM_STACK 0x4000FFFC
52 #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
53 #define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
54 #define PG_UP_TAG_AVP 0xAAAAAAAA
58 unsigned int cntr_1us;
61 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
62 #define AP20_WB_RUN_ADDRESS 0x40020000
64 #define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
65 #define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
66 #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
68 /* These are the available SKUs (product types) for Tegra */
78 /* These are the SOC categories that affect clocking */
84 TEGRA_SOC_UNKNOWN = -1,
87 #else /* __ASSEMBLY__ */
88 #define PRM_RSTCTRL TEGRA20_PMC_BASE
91 #endif /* TEGRA20_H */