2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /* Pin groups which we can set to tristate or normal */
29 /* APB_MISC_PP_TRISTATE_REG_A_0 */
66 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
103 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
140 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
161 #define TEGRA_TRISTATE_REGS 4
163 /* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
164 struct pmux_tri_ctlr {
165 uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
166 uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
167 uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
168 uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
169 uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
170 uint pmt_tri[TEGRA_TRISTATE_REGS]; /* _TRI_STATE_REG_A/B/C/D_0 14-20 */
171 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
173 uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
175 uint pmt_ctl_a; /* _PINGRP_MUX_CTL_A_0, offset 80 */
176 uint pmt_ctl_b; /* _PINGRP_MUX_CTL_B_0, offset 84 */
177 uint pmt_ctl_c; /* _PINGRP_MUX_CTL_C_0, offset 88 */
178 uint pmt_ctl_d; /* _PINGRP_MUX_CTL_D_0, offset 8C */
179 uint pmt_ctl_e; /* _PINGRP_MUX_CTL_E_0, offset 90 */
180 uint pmt_ctl_f; /* _PINGRP_MUX_CTL_F_0, offset 94 */
181 uint pmt_ctl_g; /* _PINGRP_MUX_CTL_G_0, offset 98 */
184 /* Converts a pin group to a tristate register: 0=A, 1=B, 2=C, 3=D */
185 #define TRISTATE_REG(id) ((id) >> 5)
187 /* Mask value for a tristate (within TRISTATE_REG(id)) */
188 #define TRISTATE_MASK(id) (1 << ((id) & 0x1f))
190 /* Set a pin group to tristate */
191 void pinmux_tristate_enable(enum pmux_pingrp pin);
193 /* Set a pin group to normal (non tristate) */
194 void pinmux_tristate_disable(enum pmux_pingrp pin);
196 #endif /* PINMUX_H */