1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2013
4 * NVIDIA Corporation <www.nvidia.com>
7 /* Tegra124 clock control definitions */
9 #ifndef _TEGRA124_CLOCK_H_
10 #define _TEGRA124_CLOCK_H_
12 #include <asm/arch-tegra/clock.h>
14 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
15 #define OSC_FREQ_SHIFT 28
16 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
18 /* CLK_RST_CONTROLLER_PLLC_MISC_0 */
19 #define PLLC_IDDQ (1 << 26)
21 /* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
22 #define SOR0_CLK_SEL0 (1 << 14)
23 #define SOR0_CLK_SEL1 (1 << 15)
25 int tegra_plle_enable(void);
27 void clock_sor_enable_edp_clock(void);
30 * clock_set_display_rate() - Set the display clock rate
32 * @frequency: the requested PLLD frequency
34 * Return the PLLD frequenc (which may not quite what was requested), or 0
37 u32 clock_set_display_rate(u32 frequency);
40 * clock_set_up_plldp() - Set up the EDP clock ready for use
42 void clock_set_up_plldp(void);
44 #endif /* _TEGRA124_CLOCK_H_ */