arch/arm/include/asm/arch-tegra/usb.h

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * Copyright (c) 2013 NVIDIA Corporation
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _TEGRA_USB_H_
   9 #define _TEGRA_USB_H_
  10
  11 /* USB1_LEGACY_CTRL */
  12 #define USB1_NO_LEGACY_MODE             1
  13
  14 #define VBUS_SENSE_CTL_SHIFT                    1
  15 #define VBUS_SENSE_CTL_MASK                     (3 << VBUS_SENSE_CTL_SHIFT)
  16 #define VBUS_SENSE_CTL_VBUS_WAKEUP              0
  17 #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP       1
  18 #define VBUS_SENSE_CTL_AB_SESS_VLD              2
  19 #define VBUS_SENSE_CTL_A_SESS_VLD               3
  20
  21 /* USBx_IF_USB_SUSP_CTRL_0 */
  22 #define UTMIP_PHY_ENB                           (1 << 12)
  23 #define UTMIP_RESET                             (1 << 11)
  24 #define USB_PHY_CLK_VALID                       (1 << 7)
  25 #define USB_SUSP_CLR                            (1 << 5)
  26
  27 /* USB2_IF_USB_SUSP_CTRL_0 */
  28 #define ULPI_PHY_ENB                            (1 << 13)
  29
  30 /* USBx_UTMIP_MISC_CFG0 */
  31 #define UTMIP_SUSPEND_EXIT_ON_EDGE              (1 << 22)
  32
  33 /* USBx_UTMIP_MISC_CFG1 */
  34 #define UTMIP_PLLU_STABLE_COUNT_SHIFT           6
  35 #define UTMIP_PLLU_STABLE_COUNT_MASK            \
  36                                 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
  37 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT        18
  38 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK         \
  39                                 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
  40 #define UTMIP_PHY_XTAL_CLOCKEN                  (1 << 30)
  41
  42 /* USBx_UTMIP_PLL_CFG1_0 */
  43 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT       27
  44 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK        \
  45                                 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
  46 #define UTMIP_XTAL_FREQ_COUNT_SHIFT             0
  47 #define UTMIP_XTAL_FREQ_COUNT_MASK              0xfff
  48
  49 /* USBx_UTMIP_BIAS_CFG0_0 */
  50 #define UTMIP_HSDISCON_LEVEL_MSB                (1 << 24)
  51 #define UTMIP_OTGPD                             (1 << 11)
  52 #define UTMIP_BIASPD                            (1 << 10)
  53 #define UTMIP_HSDISCON_LEVEL_SHIFT              2
  54 #define UTMIP_HSDISCON_LEVEL_MASK               \
  55                                 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
  56 #define UTMIP_HSSQUELCH_LEVEL_SHIFT             0
  57 #define UTMIP_HSSQUELCH_LEVEL_MASK              \
  58                                 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
  59
  60 /* USBx_UTMIP_BIAS_CFG1_0 */
  61 #define UTMIP_FORCE_PDTRK_POWERDOWN             1
  62 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT            3
  63 #define UTMIP_BIAS_PDTRK_COUNT_MASK             \
  64                                 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
  65
  66 /* USBx_UTMIP_DEBOUNCE_CFG0_0 */
  67 #define UTMIP_DEBOUNCE_CFG0_SHIFT               0
  68 #define UTMIP_DEBOUNCE_CFG0_MASK                0xffff
  69
  70 /* USBx_UTMIP_TX_CFG0_0 */
  71 #define UTMIP_FS_PREAMBLE_J                     (1 << 19)
  72
  73 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
  74 #define UTMIP_PD_CHRG                           1
  75
  76 /* USBx_UTMIP_SPARE_CFG0_0 */
  77 #define FUSE_SETUP_SEL                          (1 << 3)
  78
  79 /* USBx_UTMIP_HSRX_CFG0_0 */
  80 #define UTMIP_IDLE_WAIT_SHIFT                   15
  81 #define UTMIP_IDLE_WAIT_MASK                    (0x1f << UTMIP_IDLE_WAIT_SHIFT)
  82 #define UTMIP_ELASTIC_LIMIT_SHIFT               10
  83 #define UTMIP_ELASTIC_LIMIT_MASK                \
  84                                 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
  85
  86 /* USBx_UTMIP_HSRX_CFG1_0 */
  87 #define UTMIP_HS_SYNC_START_DLY_SHIFT           1
  88 #define UTMIP_HS_SYNC_START_DLY_MASK            \
  89                                 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
  90
  91 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
  92 #define IC_ENB1                                 (1 << 3)
  93
  94 /* PORTSC1, USB1, defined for Tegra20 */
  95 #define PTS1_SHIFT                              31
  96 #define PTS1_MASK                               (1 << PTS1_SHIFT)
  97 #define STS1                                    (1 << 30)
  98
  99 #define PTS_UTMI        0
 100 #define PTS_RESERVED    1
 101 #define PTS_ULPI        2
 102 #define PTS_ICUSB_SER   3
 103 #define PTS_HSIC        4
 104
 105 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
 106 #define WKOC                            (1 << 22)
 107 #define WKDS                            (1 << 21)
 108 #define WKCN                            (1 << 20)
 109
 110 /* USBx_UTMIP_XCVR_CFG0_0 */
 111 #define UTMIP_FORCE_PD_POWERDOWN                (1 << 14)
 112 #define UTMIP_FORCE_PD2_POWERDOWN               (1 << 16)
 113 #define UTMIP_FORCE_PDZI_POWERDOWN              (1 << 18)
 114 #define UTMIP_XCVR_LSBIAS_SE                    (1 << 21)
 115 #define UTMIP_XCVR_HSSLEW_MSB_SHIFT             25
 116 #define UTMIP_XCVR_HSSLEW_MSB_MASK              \
 117                         (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
 118 #define UTMIP_XCVR_SETUP_MSB_SHIFT      22
 119 #define UTMIP_XCVR_SETUP_MSB_MASK       (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
 120 #define UTMIP_XCVR_SETUP_SHIFT          0
 121 #define UTMIP_XCVR_SETUP_MASK           (0xf << UTMIP_XCVR_SETUP_SHIFT)
 122
 123 /* USBx_UTMIP_XCVR_CFG1_0 */
 124 #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT         18
 125 #define UTMIP_XCVR_TERM_RANGE_ADJ_MASK          \
 126                         (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
 127 #define UTMIP_FORCE_PDDISC_POWERDOWN            (1 << 0)
 128 #define UTMIP_FORCE_PDCHRP_POWERDOWN            (1 << 2)
 129 #define UTMIP_FORCE_PDDR_POWERDOWN              (1 << 4)
 130
 131 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
 132 #define VBUS_VLD_STS                    (1 << 26)
 133
 134 /* Setup USB on the board */
 135 int usb_process_devicetree(const void *blob);
 136
 137 #endif  /* _TEGRA_USB_H_ */