2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Portions Copyright (C) 2011-2012 NVIDIA Corporation
6 * SPDX-License-Identifier: GPL-2.0+
10 #define __TEGRA_MMC_H_
15 /* for mmc_config definition */
20 unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
21 unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
22 unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
23 unsigned int argument; /* _ARGUMENT_0 */
24 unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
25 unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
26 unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
27 unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
28 unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
29 unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
30 unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
31 unsigned int prnsts; /* _PRESENT_STATE_0 */
32 unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
33 unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
34 unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
35 unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
36 unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
37 unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
38 unsigned char swrst; /* _SW_RESET_ 31:24 */
39 unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
40 unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
41 unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
42 unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
43 unsigned char res1[2]; /* _RESERVED 31:16 */
44 unsigned int capareg; /* _CAPABILITIES_0 */
45 unsigned char res2[4]; /* RESERVED, offset 44h-47h */
46 unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
47 unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
48 unsigned short setacmd12err; /* offset 50h */
49 unsigned short setinterr; /* offset 52h */
50 unsigned char admaerr; /* offset 54h */
51 unsigned char res4[3]; /* RESERVED, offset 55h-57h */
52 unsigned long admaaddr; /* offset 58h-5Fh */
53 unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
54 unsigned short slotintstatus; /* offset FCh */
55 unsigned short hcver; /* HOST Version */
56 unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
57 unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */
58 unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */
59 unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */
60 unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */
61 unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
62 unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
63 unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
64 unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */
65 unsigned int res6[47]; /* 0x124 ~ 0x1DC */
66 unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */
67 unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */
68 unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */
69 unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */
72 #define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0)
73 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1)
74 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1)
75 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1)
77 #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
78 #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
79 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
80 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
82 #define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
83 #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
84 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
85 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
86 #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
88 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
89 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
90 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
91 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
92 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
94 #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
95 #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
96 #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
98 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
99 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
101 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
102 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
103 #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
105 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
106 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
108 #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
109 #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
110 #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
112 #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
113 #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
114 #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
115 #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
116 #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
118 #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
119 #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
120 #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
121 #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
122 #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
124 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
126 /* SDMMC1/3 settings from section 24.6 of T30 TRM */
127 #define MEMCOMP_PADCTRL_VREF 7
128 #define AUTO_CAL_ENABLED (1 << 29)
129 #define AUTO_CAL_PD_OFFSET (0x70 << 8)
130 #define AUTO_CAL_PU_OFFSET (0x62 << 0)
133 struct tegra_mmc *reg;
134 int id; /* device id/number, 0-3 */
135 int enabled; /* 1 to enable, 0 to disable */
136 int width; /* Bus Width, 1, 4 or 8 */
137 #ifndef CONFIG_TEGRA186
138 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
140 struct gpio_desc cd_gpio; /* Change Detect GPIO */
141 struct gpio_desc pwr_gpio; /* Power GPIO */
142 struct gpio_desc wp_gpio; /* Write Protect GPIO */
143 unsigned int version; /* SDHCI spec. version */
144 unsigned int clock; /* Current clock (MHz) */
145 struct mmc_config cfg; /* mmc configuration */
148 void pad_init_mmc(struct mmc_host *host);
150 #endif /* __ASSEMBLY__ */
151 #endif /* __TEGRA_MMC_H_ */