2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define NV_PA_ARM_PERIPHBASE 0x50040000
28 #define NV_PA_PG_UP_BASE 0x60000000
29 #define NV_PA_TMRUS_BASE 0x60005010
30 #define NV_PA_CLK_RST_BASE 0x60006000
31 #define NV_PA_FLOW_BASE 0x60007000
32 #define NV_PA_GPIO_BASE 0x6000D000
33 #define NV_PA_EVP_BASE 0x6000F000
34 #define NV_PA_APB_MISC_BASE 0x70000000
35 #define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
36 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
37 #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
38 #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
39 #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
40 #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
41 #define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
42 #define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
43 #define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
44 #define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
45 #define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
46 #define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
47 #define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
48 #define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
49 #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
50 #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
51 #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
52 #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
53 #define NV_PA_CSITE_BASE 0x70040000
54 #define TEGRA_USB_ADDR_MASK 0xFFFFC000
56 #define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
57 #define LOW_LEVEL_SRAM_STACK 0x4000FFFC
58 #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
59 #define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
60 #define PG_UP_TAG_AVP 0xAAAAAAAA
64 unsigned int cntr_1us;
67 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
68 #define NV_WB_RUN_ADDRESS 0x40020000
70 #define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
71 #define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
73 /* These are the available SKUs (product types) for Tegra */
81 SKU_ID_T30 = 0x81, /* Cardhu value */
85 * These are used to distinguish SOC types for setting up clocks. Mostly
86 * we can tell the clocking required by looking at the SOC sku_id, but
87 * for T30 it is a user option as to whether to run PLLP in fast or slow
88 * mode, so we have two options there.
96 TEGRA_SOC_UNKNOWN = -1,
99 #else /* __ASSEMBLY__ */
100 #define PRM_RSTCTRL NV_PA_PMC_BASE