2 * (C) Copyright 2010-2014
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA_PINMUX_H_
9 #define _TEGRA_PINMUX_H_
11 #include <asm/arch/tegra.h>
13 /* The pullup/pulldown state of a pin group */
20 /* Defines whether a pin group is tristated or in normal operation */
23 PMUX_TRI_TRISTATE = 1,
26 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
34 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
36 PMUX_PIN_LOCK_DEFAULT = 0,
37 PMUX_PIN_LOCK_DISABLE,
42 #ifdef TEGRA_PMX_PINS_HAVE_OD
44 PMUX_PIN_OD_DEFAULT = 0,
50 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
51 enum pmux_pin_ioreset {
52 PMUX_PIN_IO_RESET_DEFAULT = 0,
53 PMUX_PIN_IO_RESET_DISABLE,
54 PMUX_PIN_IO_RESET_ENABLE,
58 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
59 enum pmux_pin_rcv_sel {
60 PMUX_PIN_RCV_SEL_DEFAULT = 0,
61 PMUX_PIN_RCV_SEL_NORMAL,
62 PMUX_PIN_RCV_SEL_HIGH,
67 * This defines the configuration for a pin, including the function assigned,
68 * pull up/down settings and tristate settings. Having set up one of these
69 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
70 * available is pinmux_config_table() to configure a list of pins.
72 struct pmux_pingrp_config {
73 u32 pingrp:16; /* pin group PMUX_PINGRP_... */
74 u32 func:8; /* function to assign PMUX_FUNC_... */
75 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
76 u32 tristate:2; /* tristate or normal PMUX_TRI_... */
77 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
78 u32 io:2; /* input or output PMUX_PIN_... */
80 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
81 u32 lock:2; /* lock enable/disable PMUX_PIN... */
83 #ifdef TEGRA_PMX_PINS_HAVE_OD
84 u32 od:2; /* open-drain or push-pull driver */
86 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
87 u32 ioreset:2; /* input/output reset PMUX_PIN... */
89 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
90 u32 rcv_sel:2; /* select between High and Normal */
91 /* VIL/VIH receivers */
95 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
96 /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
97 void pinmux_set_tristate_input_clamping(void);
98 void pinmux_clear_tristate_input_clamping(void);
101 /* Set the mux function for a pin group */
102 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
104 /* Set the pull up/down feature for a pin group */
105 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
107 /* Set a pin group to tristate */
108 void pinmux_tristate_enable(enum pmux_pingrp pin);
110 /* Set a pin group to normal (non tristate) */
111 void pinmux_tristate_disable(enum pmux_pingrp pin);
113 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
114 /* Set a pin group as input or output */
115 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
119 * Configure a list of pin groups
121 * @param config List of config items
122 * @param len Number of config items in list
124 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
127 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
129 #define PMUX_SLWF_MIN 0
130 #define PMUX_SLWF_MAX 3
131 #define PMUX_SLWF_NONE -1
133 #define PMUX_SLWR_MIN 0
134 #define PMUX_SLWR_MAX 3
135 #define PMUX_SLWR_NONE -1
137 #define PMUX_DRVUP_MIN 0
138 #define PMUX_DRVUP_MAX 127
139 #define PMUX_DRVUP_NONE -1
141 #define PMUX_DRVDN_MIN 0
142 #define PMUX_DRVDN_MAX 127
143 #define PMUX_DRVDN_NONE -1
145 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
146 /* Defines a pin group cfg's low-power mode select */
156 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
157 /* Defines whether a pin group cfg's schmidt is enabled or not */
159 PMUX_SCHMT_DISABLE = 0,
160 PMUX_SCHMT_ENABLE = 1,
161 PMUX_SCHMT_NONE = -1,
165 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
166 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
168 PMUX_HSM_DISABLE = 0,
175 * This defines the configuration for a pin group's pad control config
177 struct pmux_drvgrp_config {
178 u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */
179 u32 slwf:3; /* falling edge slew */
180 u32 slwr:3; /* rising edge slew */
181 u32 drvup:8; /* pull-up drive strength */
182 u32 drvdn:8; /* pull-down drive strength */
183 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
184 u32 lpmd:3; /* low-power mode selection */
186 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
187 u32 schmt:2; /* schmidt enable */
189 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
190 u32 hsm:2; /* high-speed mode enable */
195 * Set the GP pad configs
197 * @param config List of config items
198 * @param len Number of config items in list
200 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
203 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
205 struct pmux_pingrp_desc {
207 #if defined(CONFIG_TEGRA20)
210 #endif /* CONFIG_TEGRA20 */
213 extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
215 #endif /* _TEGRA_PINMUX_H_ */