2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra clock control functions */
9 #ifndef _TEGRA_CLOCK_H_
10 #define _TEGRA_CLOCK_H_
12 /* Set of oscillator frequencies supported in the internal API. */
14 /* All in MHz, so 13_0 is 13.0MHz */
23 #include <asm/arch/clock-tables.h>
24 /* PLL stabilization delay in usec */
25 #define CLOCK_PLL_STABLE_DELAY_US 300
27 /* return the current oscillator clock frequency */
28 enum clock_osc_freq clock_get_osc_freq(void);
31 * Start PLL using the provided configuration parameters.
34 * @param divm input divider
35 * @param divn feedback divider
36 * @param divp post divider 2^n
37 * @param cpcon charge pump setup control
38 * @param lfcon loop filter setup control
40 * @returns monotonic time in us that the PLL will be stable
42 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
43 u32 divp, u32 cpcon, u32 lfcon);
46 * Set PLL output frequency
48 * @param clkid clock id
49 * @param pllout pll output id
50 * @param rate desired output rate
52 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
54 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
58 * Read low-level parameters of a PLL.
60 * @param id clock id to read (note: USB is not supported)
61 * @param divm returns input divider
62 * @param divn returns feedback divider
63 * @param divp returns post divider 2^n
64 * @param cpcon returns charge pump setup control
65 * @param lfcon returns loop filter setup control
67 * @returns 0 if ok, -1 on error (invalid clock id)
69 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
70 u32 *divp, u32 *cpcon, u32 *lfcon);
77 void clock_enable(enum periph_id clkid);
84 void clock_disable(enum periph_id clkid);
87 * Set whether a clock is enabled or disabled.
90 * @param enable 1 to enable, 0 to disable
92 void clock_set_enable(enum periph_id clkid, int enable);
95 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
96 * it out of reset and waits for th delay again.
98 * @param periph_id peripheral to reset
99 * @param us_delay time to delay in microseconds
101 void reset_periph(enum periph_id periph_id, int us_delay);
104 * Put a peripheral into or out of reset.
106 * @param periph_id peripheral to reset
107 * @param enable 1 to put into reset, 0 to take out of reset
109 void reset_set_enable(enum periph_id periph_id, int enable);
112 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
114 /* Things we can hold in reset for each CPU */
116 crc_rst_de = 1 << 2, /* What is de? */
117 crc_rst_watchdog = 1 << 3,
118 crc_rst_debug = 1 << 4,
122 * Put parts of the CPU complex into or out of reset.\
124 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
125 * @param which which parts of the complex to affect (OR of crc_reset_id)
126 * @param reset 1 to assert reset, 0 to de-assert
128 void reset_cmplx_set_enable(int cpu, int which, int reset);
131 * Set the source for a peripheral clock. This plus the divisor sets the
132 * clock rate. You need to look up the datasheet to see the meaning of the
133 * source parameter as it changes for each peripheral.
135 * Warning: This function is only for use pre-relocation. Please use
136 * clock_start_periph_pll() instead.
138 * @param periph_id peripheral to adjust
139 * @param source source clock (0, 1, 2 or 3)
141 void clock_ll_set_source(enum periph_id periph_id, unsigned source);
144 * Set the source and divisor for a peripheral clock. This sets the
145 * clock rate. You need to look up the datasheet to see the meaning of the
146 * source parameter as it changes for each peripheral.
148 * Warning: This function is only for use pre-relocation. Please use
149 * clock_start_periph_pll() instead.
151 * @param periph_id peripheral to adjust
152 * @param source source clock (0, 1, 2 or 3)
153 * @param divisor divisor value to use
155 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
159 * Start a peripheral PLL clock at the given rate. This also resets the
162 * @param periph_id peripheral to start
163 * @param parent PLL id of required parent clock
164 * @param rate Required clock rate in Hz
165 * @return rate selected in Hz, or -1U if something went wrong
167 unsigned clock_start_periph_pll(enum periph_id periph_id,
168 enum clock_id parent, unsigned rate);
171 * Returns the rate of a peripheral clock in Hz. Since the caller almost
172 * certainly knows the parent clock (having just set it) we require that
173 * this be passed in so we don't need to work it out.
175 * @param periph_id peripheral to start
176 * @param parent PLL id of parent clock (used to calculate rate, you
178 * @return clock rate of peripheral in Hz
180 unsigned long clock_get_periph_rate(enum periph_id periph_id,
181 enum clock_id parent);
184 * Adjust peripheral PLL clock to the given rate. This does not reset the
185 * peripheral. If a second stage divisor is not available, pass NULL for
186 * extra_div. If it is available, then this parameter will return the
187 * divisor selected (which will be a power of 2 from 1 to 256).
189 * @param periph_id peripheral to start
190 * @param parent PLL id of required parent clock
191 * @param rate Required clock rate in Hz
192 * @param extra_div value for the second-stage divisor (NULL if one is
194 * @return rate selected in Hz, or -1U if something went wrong
196 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
197 enum clock_id parent, unsigned rate, int *extra_div);
200 * Returns the clock rate of a specified clock, in Hz.
202 * @param parent PLL id of clock to check
203 * @return rate of clock in Hz
205 unsigned clock_get_rate(enum clock_id clkid);
208 * Start up a UART using low-level calls
210 * Prior to relocation clock_start_periph_pll() cannot be called. This
211 * function provides a way to set up a UART using low-level calls which
212 * do not require BSS.
214 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
216 void clock_ll_start_uart(enum periph_id periph_id);
219 * Decode a peripheral ID from a device tree node.
221 * This works by looking up the peripheral's 'clocks' node and reading out
222 * the second cell, which is the clock number / peripheral ID.
224 * @param blob FDT blob to use
225 * @param node Node to look at
226 * @return peripheral ID, or PERIPH_ID_NONE if none
228 enum periph_id clock_decode_periph_id(const void *blob, int node);
231 * Checks if the oscillator bypass is enabled (XOBP bit)
233 * @return 1 if bypass is enabled, 0 if not
235 int clock_get_osc_bypass(void);
238 * Checks that clocks are valid and prints a warning if not
240 * @return 0 if ok, -1 on error
242 int clock_verify(void);
244 /* Initialize the clocks */
245 void clock_init(void);
247 /* Initialize the PLLs */
248 void clock_early_init(void);
250 /* Returns a pointer to the clock source register for a peripheral */
251 u32 *get_periph_source_reg(enum periph_id periph_id);
254 * Given a peripheral ID and the required source clock, this returns which
255 * value should be programmed into the source mux for that peripheral.
257 * There is special code here to handle the one source type with 5 sources.
259 * @param periph_id peripheral to start
260 * @param source PLL id of required parent clock
261 * @param mux_bits Set to number of bits in mux register: 2 or 4
262 * @param divider_bits Set to number of divider bits (8 or 16)
263 * @return mux value (0-4, or -1 if not found)
265 int get_periph_clock_source(enum periph_id periph_id,
266 enum clock_id parent, int *mux_bits, int *divider_bits);
269 * Convert a device tree clock ID to our peripheral ID. They are mostly
270 * the same but we are very cautious so we check that a valid clock ID is
273 * @param clk_id Clock ID according to tegra30 device tree binding
274 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
276 enum periph_id clk_id_to_periph_id(int clk_id);
279 * Set the output frequency you want for each PLL clock.
280 * PLL output frequencies are programmed by setting their N, M and P values.
281 * The governing equations are:
282 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
283 * where Fo is the output frequency from the PLL.
284 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
285 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
286 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
288 * @param n PLL feedback divider(DIVN)
289 * @param m PLL input divider(DIVN)
290 * @param p post divider(DIVP)
291 * @param cpcon base PLL charge pump(CPCON)
292 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
293 * be overriden), 1 if PLL is already correct
295 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
297 /* return 1 if a peripheral ID is in range */
298 #define clock_type_id_isvalid(id) ((id) >= 0 && \
299 (id) < CLOCK_TYPE_COUNT)
301 /* return 1 if a periphc_internal_id is in range */
302 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
303 (id) < PERIPHC_COUNT)
305 /* SoC-specific TSC init */
306 void arch_timer_init(void);
308 #endif /* _TEGRA_CLOCK_H_ */