ddb71c1bbd33f71e054ab2fc50834c90061cc8e3
[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-sunxi / display.h
1 /*
2  * Sunxi platform display controller register and constant defines
3  *
4  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef _SUNXI_DISPLAY_H
10 #define _SUNXI_DISPLAY_H
11
12 struct sunxi_de_be_reg {
13         u8 res0[0x800];                 /* 0x000 */
14         u32 mode;                       /* 0x800 */
15         u32 backcolor;                  /* 0x804 */
16         u32 disp_size;                  /* 0x808 */
17         u8 res1[0x4];                   /* 0x80c */
18         u32 layer0_size;                /* 0x810 */
19         u32 layer1_size;                /* 0x814 */
20         u32 layer2_size;                /* 0x818 */
21         u32 layer3_size;                /* 0x81c */
22         u32 layer0_pos;                 /* 0x820 */
23         u32 layer1_pos;                 /* 0x824 */
24         u32 layer2_pos;                 /* 0x828 */
25         u32 layer3_pos;                 /* 0x82c */
26         u8 res2[0x10];                  /* 0x830 */
27         u32 layer0_stride;              /* 0x840 */
28         u32 layer1_stride;              /* 0x844 */
29         u32 layer2_stride;              /* 0x848 */
30         u32 layer3_stride;              /* 0x84c */
31         u32 layer0_addr_low32b;         /* 0x850 */
32         u32 layer1_addr_low32b;         /* 0x854 */
33         u32 layer2_addr_low32b;         /* 0x858 */
34         u32 layer3_addr_low32b;         /* 0x85c */
35         u32 layer0_addr_high4b;         /* 0x860 */
36         u32 layer1_addr_high4b;         /* 0x864 */
37         u32 layer2_addr_high4b;         /* 0x868 */
38         u32 layer3_addr_high4b;         /* 0x86c */
39         u32 reg_ctrl;                   /* 0x870 */
40         u8 res3[0xc];                   /* 0x874 */
41         u32 color_key_max;              /* 0x880 */
42         u32 color_key_min;              /* 0x884 */
43         u32 color_key_config;           /* 0x888 */
44         u8 res4[0x4];                   /* 0x88c */
45         u32 layer0_attr0_ctrl;          /* 0x890 */
46         u32 layer1_attr0_ctrl;          /* 0x894 */
47         u32 layer2_attr0_ctrl;          /* 0x898 */
48         u32 layer3_attr0_ctrl;          /* 0x89c */
49         u32 layer0_attr1_ctrl;          /* 0x8a0 */
50         u32 layer1_attr1_ctrl;          /* 0x8a4 */
51         u32 layer2_attr1_ctrl;          /* 0x8a8 */
52         u32 layer3_attr1_ctrl;          /* 0x8ac */
53 };
54
55 struct sunxi_lcdc_reg {
56         u32 ctrl;                       /* 0x00 */
57         u32 int0;                       /* 0x04 */
58         u32 int1;                       /* 0x08 */
59         u8 res0[0x04];                  /* 0x0c */
60         u32 frame_ctrl;                 /* 0x10 */
61         u8 res1[0x2c];                  /* 0x14 */
62         u32 tcon0_ctrl;                 /* 0x40 */
63         u32 tcon0_dclk;                 /* 0x44 */
64         u32 tcon0_basic_timing0;        /* 0x48 */
65         u32 tcon0_basic_timing1;        /* 0x4c */
66         u32 tcon0_basic_timing2;        /* 0x50 */
67         u32 tcon0_basic_timing3;        /* 0x54 */
68         u32 tcon0_hv_intf;              /* 0x58 */
69         u8 res2[0x04];                  /* 0x5c */
70         u32 tcon0_cpu_intf;             /* 0x60 */
71         u32 tcon0_cpu_wr_dat;           /* 0x64 */
72         u32 tcon0_cpu_rd_dat0;          /* 0x68 */
73         u32 tcon0_cpu_rd_dat1;          /* 0x6c */
74         u32 tcon0_ttl_timing0;          /* 0x70 */
75         u32 tcon0_ttl_timing1;          /* 0x74 */
76         u32 tcon0_ttl_timing2;          /* 0x78 */
77         u32 tcon0_ttl_timing3;          /* 0x7c */
78         u32 tcon0_ttl_timing4;          /* 0x80 */
79         u32 tcon0_lvds_intf;            /* 0x84 */
80         u32 tcon0_io_polarity;          /* 0x88 */
81         u32 tcon0_io_tristate;          /* 0x8c */
82         u32 tcon1_ctrl;                 /* 0x90 */
83         u32 tcon1_timing_source;        /* 0x94 */
84         u32 tcon1_timing_scale;         /* 0x98 */
85         u32 tcon1_timing_out;           /* 0x9c */
86         u32 tcon1_timing_h;             /* 0xa0 */
87         u32 tcon1_timing_v;             /* 0xa4 */
88         u32 tcon1_timing_sync;          /* 0xa8 */
89         u8 res3[0x44];                  /* 0xac */
90         u32 tcon1_io_polarity;          /* 0xf0 */
91         u32 tcon1_io_tristate;          /* 0xf4 */
92 };
93
94 struct sunxi_hdmi_reg {
95         u32 version_id;                 /* 0x000 */
96         u32 ctrl;                       /* 0x004 */
97         u32 irq;                        /* 0x008 */
98         u32 hpd;                        /* 0x00c */
99         u32 video_ctrl;                 /* 0x010 */
100         u32 video_size;                 /* 0x014 */
101         u32 video_bp;                   /* 0x018 */
102         u32 video_fp;                   /* 0x01c */
103         u32 video_spw;                  /* 0x020 */
104         u32 video_polarity;             /* 0x024 */
105         u8 res0[0x1d8];                 /* 0x028 */
106         u32 pad_ctrl0;                  /* 0x200 */
107         u32 pad_ctrl1;                  /* 0x204 */
108         u32 pll_ctrl;                   /* 0x208 */
109         u32 pll_dbg0;                   /* 0x20c */
110 };
111
112 /*
113  * DE-BE register constants.
114  */
115 #define SUNXI_DE_BE_WIDTH(x)                    (((x) - 1) << 0)
116 #define SUNXI_DE_BE_HEIGHT(y)                   (((y) - 1) << 16)
117 #define SUNXI_DE_BE_MODE_ENABLE                 (1 << 0)
118 #define SUNXI_DE_BE_MODE_START                  (1 << 1)
119 #define SUNXI_DE_BE_MODE_LAYER0_ENABLE          (1 << 8)
120 #define SUNXI_DE_BE_LAYER_STRIDE(x)             ((x) << 5)
121 #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS          (1 << 0)
122 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888    (0x09 << 8)
123
124 /*
125  * LCDC register constants.
126  */
127 #define SUNXI_LCDC_X(x)                         (((x) - 1) << 16)
128 #define SUNXI_LCDC_Y(y)                         (((y) - 1) << 0)
129 #define SUNXI_LCDC_CTRL_IO_MAP_MASK             (1 << 0)
130 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0            (0 << 0)
131 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1            (1 << 0)
132 #define SUNXI_LCDC_CTRL_TCON_ENABLE             (1 << 31)
133 #define SUNXI_LCDC_TCON0_DCLK_ENABLE            (0xf << 28)
134 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)      (((n) & 0x1f) << 4)
135 #define SUNXI_LCDC_TCON1_CTRL_ENABLE            (1 << 31)
136 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n)         (((n) - 1) << 0)
137 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)      (((n) - 1) << 16)
138 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n)         (((n) - 1) << 0)
139 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)      (((n) * 2) << 16)
140
141 /*
142  * HDMI register constants.
143  */
144 #define SUNXI_HDMI_X(x)                         (((x) - 1) << 0)
145 #define SUNXI_HDMI_Y(y)                         (((y) - 1) << 16)
146 #define SUNXI_HDMI_CTRL_ENABLE                  (1 << 31)
147 #define SUNXI_HDMI_IRQ_STATUS_FIFO_UF           (1 << 0)
148 #define SUNXI_HDMI_IRQ_STATUS_FIFO_OF           (1 << 1)
149 #define SUNXI_HDMI_IRQ_STATUS_BITS              0x73
150 #define SUNXI_HDMI_HPD_DETECT                   (1 << 0)
151 #define SUNXI_HDMI_VIDEO_CTRL_ENABLE            (1 << 31)
152 #define SUNXI_HDMI_VIDEO_POL_HOR                (1 << 0)
153 #define SUNXI_HDMI_VIDEO_POL_VER                (1 << 1)
154 #define SUNXI_HDMI_VIDEO_POL_TX_CLK             (0x3e0 << 16)
155
156 #ifdef CONFIG_MACH_SUN6I
157 #define SUNXI_HDMI_PAD_CTRL0_HDP                0x7e80000f
158 #define SUNXI_HDMI_PAD_CTRL0_RUN                0x7e8000ff
159 #else
160 #define SUNXI_HDMI_PAD_CTRL0_HDP                0xfe800000
161 #define SUNXI_HDMI_PAD_CTRL0_RUN                0xfe800000
162 #endif
163
164 #ifdef CONFIG_MACH_SUN4I
165 #define SUNXI_HDMI_PAD_CTRL1                    0x00d8c820
166 #elif defined CONFIG_MACH_SUN6I
167 #define SUNXI_HDMI_PAD_CTRL1                    0x01ded030
168 #else
169 #define SUNXI_HDMI_PAD_CTRL1                    0x00d8c830
170 #endif
171 #define SUNXI_HDMI_PAD_CTRL1_HALVE              (1 << 6)
172
173 #ifdef CONFIG_MACH_SUN6I
174 #define SUNXI_HDMI_PLL_CTRL                     0xba48a308
175 #define SUNXI_HDMI_PLL_CTRL_DIV(n)              (((n) - 1) << 4)
176 #else
177 #define SUNXI_HDMI_PLL_CTRL                     0xfa4ef708
178 #define SUNXI_HDMI_PLL_CTRL_DIV(n)              ((n) << 4)
179 #endif
180 #define SUNXI_HDMI_PLL_CTRL_DIV_MASK            (0xf << 4)
181
182 #define SUNXI_HDMI_PLL_DBG0_PLL3                (0 << 21)
183 #define SUNXI_HDMI_PLL_DBG0_PLL7                (1 << 21)
184
185 int sunxi_simplefb_setup(void *blob);
186
187 #endif /* _SUNXI_DISPLAY_H */