1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * sun4i, sun5i and sun7i clock register definitions
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
10 #ifndef _SUNXI_CLOCK_SUN4I_H
11 #define _SUNXI_CLOCK_SUN4I_H
13 struct sunxi_ccm_reg {
14 u32 pll1_cfg; /* 0x00 pll1 control */
15 u32 pll1_tun; /* 0x04 pll1 tuning */
16 u32 pll2_cfg; /* 0x08 pll2 control */
17 u32 pll2_tun; /* 0x0c pll2 tuning */
18 u32 pll3_cfg; /* 0x10 pll3 control */
20 u32 pll4_cfg; /* 0x18 pll4 control */
22 u32 pll5_cfg; /* 0x20 pll5 control */
23 u32 pll5_tun; /* 0x24 pll5 tuning */
24 u32 pll6_cfg; /* 0x28 pll6 control */
25 u32 pll6_tun; /* 0x2c pll6 tuning */
26 u32 pll7_cfg; /* 0x30 pll7 control */
27 u32 pll1_tun2; /* 0x34 pll5 tuning2 */
29 u32 pll5_tun2; /* 0x3c pll5 tuning2 */
31 u32 pll_lock_dbg; /* 0x4c pll lock time debug */
32 u32 osc24m_cfg; /* 0x50 osc24m control */
33 u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
34 u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
35 u32 axi_gate; /* 0x5c axi module clock gating */
36 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
37 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
38 u32 apb0_gate; /* 0x68 apb0 module clock gating */
39 u32 apb1_gate; /* 0x6c apb1 module clock gating */
41 u32 nand0_clk_cfg; /* 0x80 nand sub clock control */
42 u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
43 u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
44 u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
45 u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
46 u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
47 u32 ts_clk_cfg; /* 0x98 transport stream clock control */
48 u32 ss_clk_cfg; /* 0x9c */
49 u32 spi0_clk_cfg; /* 0xa0 */
50 u32 spi1_clk_cfg; /* 0xa4 */
51 u32 spi2_clk_cfg; /* 0xa8 */
52 u32 pata_clk_cfg; /* 0xac */
53 u32 ir0_clk_cfg; /* 0xb0 */
54 u32 ir1_clk_cfg; /* 0xb4 */
55 u32 iis_clk_cfg; /* 0xb8 */
56 u32 ac97_clk_cfg; /* 0xbc */
57 u32 spdif_clk_cfg; /* 0xc0 */
58 u32 keypad_clk_cfg; /* 0xc4 */
59 u32 sata_clk_cfg; /* 0xc8 */
60 u32 usb_clk_cfg; /* 0xcc */
61 u32 gps_clk_cfg; /* 0xd0 */
62 u32 spi3_clk_cfg; /* 0xd4 */
64 u32 dram_clk_gate; /* 0x100 */
65 u32 be0_clk_cfg; /* 0x104 */
66 u32 be1_clk_cfg; /* 0x108 */
67 u32 fe0_clk_cfg; /* 0x10c */
68 u32 fe1_clk_cfg; /* 0x110 */
69 u32 mp_clk_cfg; /* 0x114 */
70 u32 lcd0_ch0_clk_cfg; /* 0x118 */
71 u32 lcd1_ch0_clk_cfg; /* 0x11c */
72 u32 csi_isp_clk_cfg; /* 0x120 */
74 u32 tvd_clk_reg; /* 0x128 */
75 u32 lcd0_ch1_clk_cfg; /* 0x12c */
76 u32 lcd1_ch1_clk_cfg; /* 0x130 */
77 u32 csi0_clk_cfg; /* 0x134 */
78 u32 csi1_clk_cfg; /* 0x138 */
79 u32 ve_clk_cfg; /* 0x13c */
80 u32 audio_codec_clk_cfg; /* 0x140 */
81 u32 avs_clk_cfg; /* 0x144 */
82 u32 ace_clk_cfg; /* 0x148 */
83 u32 lvds_clk_cfg; /* 0x14c */
84 u32 hdmi_clk_cfg; /* 0x150 */
85 u32 mali_clk_cfg; /* 0x154 */
87 u32 mbus_clk_cfg; /* 0x15c */
89 u32 gmac_clk_cfg; /* 0x164 */
93 #define APB1_CLK_SRC_OSC24M (0x0 << 24)
94 #define APB1_CLK_SRC_PLL6 (0x1 << 24)
95 #define APB1_CLK_SRC_LOSC (0x2 << 24)
96 #define APB1_CLK_SRC_MASK (0x3 << 24)
97 #define APB1_CLK_RATE_N_1 (0x0 << 16)
98 #define APB1_CLK_RATE_N_2 (0x1 << 16)
99 #define APB1_CLK_RATE_N_4 (0x2 << 16)
100 #define APB1_CLK_RATE_N_8 (0x3 << 16)
101 #define APB1_CLK_RATE_N_MASK (3 << 16)
102 #define APB1_CLK_RATE_M(m) (((m)-1) << 0)
103 #define APB1_CLK_RATE_M_MASK (0x1f << 0)
105 /* apb1 gate field */
106 #define APB1_GATE_UART_SHIFT (16)
107 #define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
108 #define APB1_GATE_TWI_SHIFT (0)
109 #define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
112 #define AXI_DIV_SHIFT (0)
117 #define AHB_DIV_SHIFT (4)
122 #define APB0_DIV_SHIFT (8)
127 #define CPU_CLK_SRC_SHIFT (16)
128 #define CPU_CLK_SRC_OSC24M 1
129 #define CPU_CLK_SRC_PLL1 2
131 #define CCM_PLL1_CFG_ENABLE_SHIFT 31
132 #define CCM_PLL1_CFG_VCO_RST_SHIFT 30
133 #define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26
134 #define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25
135 #define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20
136 #define CCM_PLL1_CFG_DIVP_SHIFT 16
137 #define CCM_PLL1_CFG_LCK_TMR_SHIFT 13
138 #define CCM_PLL1_CFG_FACTOR_N_SHIFT 8
139 #define CCM_PLL1_CFG_FACTOR_K_SHIFT 4
140 #define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3
141 #define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2
142 #define CCM_PLL1_CFG_FACTOR_M_SHIFT 0
144 #define PLL1_CFG_DEFAULT 0xa1005000
146 #if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
148 * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
149 * halving the mbus frequency, so set it to 300 MHz ourselves and base the
150 * mbus divider on that.
152 #define PLL6_CFG_DEFAULT 0xa1009900
154 #define PLL6_CFG_DEFAULT 0xa1009911
158 #define NAND_CLK_SRC_OSC24 0
159 #define NAND_CLK_DIV_N 0
160 #define NAND_CLK_DIV_M 0
163 #define GPS_SCLK_GATING_OFF 0
166 /* ahb clock gate bit offset */
167 #define AHB_GATE_OFFSET_GPS 26
168 #define AHB_GATE_OFFSET_SATA 25
169 #define AHB_GATE_OFFSET_PATA 24
170 #define AHB_GATE_OFFSET_SPI3 23
171 #define AHB_GATE_OFFSET_SPI2 22
172 #define AHB_GATE_OFFSET_SPI1 21
173 #define AHB_GATE_OFFSET_SPI0 20
174 #define AHB_GATE_OFFSET_TS0 18
175 #define AHB_GATE_OFFSET_EMAC 17
176 #define AHB_GATE_OFFSET_ACE 16
177 #define AHB_GATE_OFFSET_DLL 15
178 #define AHB_GATE_OFFSET_SDRAM 14
179 #define AHB_GATE_OFFSET_NAND0 13
180 #define AHB_GATE_OFFSET_MS 12
181 #define AHB_GATE_OFFSET_MMC3 11
182 #define AHB_GATE_OFFSET_MMC2 10
183 #define AHB_GATE_OFFSET_MMC1 9
184 #define AHB_GATE_OFFSET_MMC0 8
185 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
186 #define AHB_GATE_OFFSET_BIST 7
187 #define AHB_GATE_OFFSET_DMA 6
188 #define AHB_GATE_OFFSET_SS 5
189 #define AHB_GATE_OFFSET_USB_OHCI1 4
190 #define AHB_GATE_OFFSET_USB_EHCI1 3
191 #define AHB_GATE_OFFSET_USB_OHCI0 2
192 #define AHB_GATE_OFFSET_USB_EHCI0 1
193 #define AHB_GATE_OFFSET_USB0 0
195 /* ahb clock gate bit offset (second register) */
196 #define AHB_GATE_OFFSET_GMAC 17
197 #define AHB_GATE_OFFSET_DE_FE0 14
198 #define AHB_GATE_OFFSET_DE_BE0 12
199 #define AHB_GATE_OFFSET_HDMI 11
200 #define AHB_GATE_OFFSET_LCD1 5
201 #define AHB_GATE_OFFSET_LCD0 4
202 #define AHB_GATE_OFFSET_TVE1 3
203 #define AHB_GATE_OFFSET_TVE0 2
205 #define CCM_AHB_GATE_GPS (0x1 << 26)
206 #define CCM_AHB_GATE_SDRAM (0x1 << 14)
207 #define CCM_AHB_GATE_DLL (0x1 << 15)
208 #define CCM_AHB_GATE_ACE (0x1 << 16)
210 #define CCM_PLL3_CTRL_M_SHIFT 0
211 #define CCM_PLL3_CTRL_M_MASK (0x7f << CCM_PLL3_CTRL_M_SHIFT)
212 #define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0)
213 #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15)
214 #define CCM_PLL3_CTRL_EN (0x1 << 31)
216 #define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
217 #define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
218 #define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
219 #define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
220 #define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
221 #define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
222 #define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
223 #define CCM_PLL5_CTRL_K_SHIFT 4
224 #define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
225 #define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
226 #define CCM_PLL5_CTRL_LDO (0x1 << 7)
227 #define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
228 #define CCM_PLL5_CTRL_N_SHIFT 8
229 #define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
230 #define CCM_PLL5_CTRL_N_X(n) (n)
231 #define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
232 #define CCM_PLL5_CTRL_P_SHIFT 16
233 #define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
234 #define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
235 #define CCM_PLL5_CTRL_BW (0x1 << 18)
236 #define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
237 #define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
238 #define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
239 #define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
240 #define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
241 #define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
242 #define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
243 #define CCM_PLL5_CTRL_EN (0x1 << 31)
245 #define CCM_PLL6_CTRL_EN 31
246 #define CCM_PLL6_CTRL_BYPASS_EN 30
247 #define CCM_PLL6_CTRL_SATA_EN_SHIFT 14
248 #define CCM_PLL6_CTRL_N_SHIFT 8
249 #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
250 #define CCM_PLL6_CTRL_K_SHIFT 4
251 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
253 #define CCM_GPS_CTRL_RESET (0x1 << 0)
254 #define CCM_GPS_CTRL_GATE (0x1 << 1)
256 #define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
258 #define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
259 #define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
260 #define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
261 #define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
262 #define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
263 #define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
264 #define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
265 #define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
266 #define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
267 #define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
268 #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
269 #define CCM_MBUS_CTRL_GATE (0x1 << 31)
271 #define CCM_NAND_CTRL_M(x) ((x) - 1)
272 #define CCM_NAND_CTRL_N(x) ((x) << 16)
273 #define CCM_NAND_CTRL_OSCM24 (0x0 << 24)
274 #define CCM_NAND_CTRL_PLL6 (0x1 << 24)
275 #define CCM_NAND_CTRL_PLL5 (0x2 << 24)
276 #define CCM_NAND_CTRL_ENABLE (0x1 << 31)
278 #define CCM_MMC_CTRL_M(x) ((x) - 1)
279 #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
280 #define CCM_MMC_CTRL_N(x) ((x) << 16)
281 #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
282 #define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
283 #define CCM_MMC_CTRL_PLL6 (0x1 << 24)
284 #define CCM_MMC_CTRL_PLL5 (0x2 << 24)
285 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
287 #define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */
288 #define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */
289 #define CCM_DRAM_GATE_OFFSET_DE_BE0 26
290 #define CCM_DRAM_GATE_OFFSET_DE_BE1 27
292 #define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
293 #define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
294 #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
295 #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
296 #define CCM_LCD_CH0_CTRL_MIPI_PLL 0 /* No mipi pll on sun4i/5i/7i */
297 #ifdef CONFIG_MACH_SUN5I
298 #define CCM_LCD_CH0_CTRL_TVE_RST (0x1 << 29)
300 #define CCM_LCD_CH0_CTRL_TVE_RST 0 /* No separate tve-rst on sun4i/7i */
302 #define CCM_LCD_CH0_CTRL_RST (0x1 << 30)
303 #define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
305 #define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
306 #define CCM_LCD_CH1_CTRL_HALF_SCLK1 (1 << 11)
307 #define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
308 #define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
309 #define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
310 #define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
311 /* Enable / disable both ch1 sclk1 and sclk2 at the same time */
312 #define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15)
314 #define CCM_LVDS_CTRL_RST (1 << 0)
316 #define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
317 #define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
318 #define CCM_HDMI_CTRL_PLL3 (0 << 24)
319 #define CCM_HDMI_CTRL_PLL7 (1 << 24)
320 #define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
321 #define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
322 /* No separate ddc gate on sun4i, sun5i and sun7i */
323 #define CCM_HDMI_CTRL_DDC_GATE 0
324 #define CCM_HDMI_CTRL_GATE (0x1 << 31)
326 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
327 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
328 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
329 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
330 #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
331 #define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
332 #define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
334 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
335 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
336 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
337 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6)
338 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7)
339 #define CCM_USB_CTRL_PHYGATE (0x1 << 8)
340 /* These 3 are sun6i only, define them as 0 on sun4i */
341 #define CCM_USB_CTRL_PHY0_CLK 0
342 #define CCM_USB_CTRL_PHY1_CLK 0
343 #define CCM_USB_CTRL_PHY2_CLK 0
345 /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
346 #define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
347 #define CCM_DE_CTRL_PLL_MASK (3 << 24)
348 #define CCM_DE_CTRL_PLL3 (0 << 24)
349 #define CCM_DE_CTRL_PLL7 (1 << 24)
350 #define CCM_DE_CTRL_PLL5P (2 << 24)
351 #define CCM_DE_CTRL_RST (1 << 30)
352 #define CCM_DE_CTRL_GATE (1 << 31)
355 void clock_set_pll1(unsigned int hz);
356 void clock_set_pll3(unsigned int hz);
357 unsigned int clock_get_pll3(void);
358 unsigned int clock_get_pll5p(void);
359 unsigned int clock_get_pll6(void);
362 #endif /* _SUNXI_CLOCK_SUN4I_H */