1 /******************************************************************************
2 ** File Name: sprd_module_config.h *
5 ** Copyright: 2010 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 07/08/2010 Tim.Luo Create. *
13 ******************************************************************************/
14 #ifndef _SPRD_MODULE_CONFIG_H_
15 #define _SPRD_MODULE_CONFIG_H_
16 /*----------------------------------------------------------------------------*
18 **------------------------------------------------------------------------- */
20 /**---------------------------------------------------------------------------*
22 **--------------------------------------------------------------------------*/
27 /**---------------------------------------------------------------------------*
29 **---------------------------------------------------------------------------*/
30 #define WDG_INIT_COUNT (0x0009FFFF) //uint : 1/32768s
31 /**---------------------------------------------------------------------------*
32 ** Macro Define for bus monitor **
33 **---------------------------------------------------------------------------*/
34 #define MAX_BM_POINTS_NUM 2
36 /**---------------------------------------------------------------------------*
37 ** Macro Define for kpd **
38 **---------------------------------------------------------------------------*/
39 #define KPD_ROW_NUM 8 // KPD_ROW_MIN_NUM <= value <= KPD_ROW_MAX_NUM changed by yong.zou
40 #define KPD_COL_NUM 8 // KPD_COL_MIN_NUM <= value <= KPD_COL_MAX_NUM changed by yong.zou
42 #define CFG_ROW_POLARITY (0x00FF & KPDPOLARITY_ROW)
43 #define CFG_COL_POLARITY (0xFF00 & KPDPOLARITY_COL)
46 #define MAX_MUL_KEY_NUM 4
48 #ifdef KEYPAD_TYPE_QWERTY_KEYPAD
49 #define KPD_NUM ((0x0F << 16) | (0x1F << 20))//KPDCTL_KPD ;// 8*8
51 #define KPD_NUM ((0x01 << 16) | (0x03 << 20))//KPDCTL_KPD ;// 5*5
54 #define KPD_NUM (0x31 << 16)
56 /**---------------------------------------------------------------------------*
57 ** Macro Define for pwm **
58 **---------------------------------------------------------------------------*/
60 #define PWMx_BASE(x) (PWM_BASE + (x)*0x20 )
62 #define GEN_PWM GR_CLK_EN
63 #define GEN_PWMx(x) (CLK_PWM0_EN << (x))
65 // the prescale = 0, and the mod = 10
66 #define PWM_MAX_FREQ( _pwm_clk ) ( (_pwm_clk) / 10 )
67 #define PWM_MIN_FREQ( _pwm_clk ) ( (_pwm_clk) / 256 / 256 )
68 /**---------------------------------------------------------------------------*
69 ** Macro Define for spi **
70 **---------------------------------------------------------------------------*/
73 #define MAX_SPI_PORT_NUM (1UL)
75 #define SPI_TX_WATERMARK 0x28
76 #define SPI_RX_WATERMARK 0x28
78 #define SPI_TX_CHANNEL 19
79 #define SPI_RX_CHANNEL 20
81 #define SPI_DMA_TIME_OUT 0x80000
82 #define SPI_BURST_SIZE 16
83 #define SPI_BURST_SIZE_MARK 0xF
84 #define LENGTH_4_DIVIDE 4
86 #define SPI_RX_FIFO_FULL BIT_0
87 #define SPI_RX_FIFO_EMPTY BIT_1
88 #define SPI_TX_FIFO_FULL BIT_2
89 #define SPI_TX_FIFO_EMPTY BIT_3
90 #define SPI_RX_FIFO_REALLY_FULL BIT_4
91 #define SPI_RX_FIFO_REALLY_EMPTY BIT_5
92 #define SPI_TX_FIFO_REALLY_FULL BIT_6
93 #define SPI_TX_FIFO_REALLY_EMPTY BIT_7
95 /**---------------------------------------------------------------------------*
96 ** Macro Define for adc/tpc **
97 **---------------------------------------------------------------------------*/
99 #define ADC_SCALE_3V SCI_FALSE
100 #define ADC_SCALE_1V2 SCI_TRUE
102 #define TPC_CHANNEL_X 2
103 #define TPC_CHANNEL_Y 3
104 #define ADC_CHANNEL_PROG 4
105 #define ADC_CHANNEL_VBAT 5
106 #define ADC_CHANNEL_VCHG 6
108 /**---------------------------------------------------------------------------*
109 ** Macro Define for GPIO **
110 **---------------------------------------------------------------------------*/
111 #define GPIO_INVALID_ID 0x0FF
112 #define GPIO_MAX_PIN_NUM 271
113 #define GPIO_MAX_REC_NUM 10
116 /**---------------------------------------------------------------------------*
117 ** Micro Define for SDIO **
118 **---------------------------------------------------------------------------*/
119 #define SDIO_BASE_CLK_384M 384000000 // 384 MHz
120 #define SDIO_BASE_CLK_312M 312000000 // 312 MHz
121 #define SDIO_BASE_CLK_256M 256000000 // 256 MHz
122 #define SDIO_BASE_CLK_192M 192000000 // 192 MHz
123 #define SDIO_BASE_CLK_153M 153000000 // 153 MHz
124 #define SDIO_BASE_CLK_96M 96000000 // 96 MHz
125 #define SDIO_BASE_CLK_80M 80000000 // 80 MHz
126 #define SDIO_BASE_CLK_64M 64000000 // 64 MHz
127 #define SDIO_BASE_CLK_50M 50000000 // 50 MHz ,should cfg MPLL to 300/350/400???
128 #define SDIO_BASE_CLK_48M 48000000 // 48 MHz
129 #define SDIO_BASE_CLK_40M 40000000 // 40 MHz
130 #define SDIO_BASE_CLK_32M 32000000 // 32 MHz
131 #define SDIO_BASE_CLK_26M 26000000 // 26 MHz
132 #define SDIO_BASE_CLK_25M 25000000 // 25 MHz
133 #define SDIO_BASE_CLK_20M 20000000 // 20 MHz
134 #define SDIO_BASE_CLK_16M 16000000 // 16 MHz
135 #define SDIO_BASE_CLK_8M 8000000 // 8 MHz
137 #define SDIO_CLK_50M 50000000 // 50 MHz, 1 div for 50MHz
138 #define SDIO_CLK_48M 48000000 // 48 MHz
139 #define SDIO_CLK_40M 40000000 // 40 MHz
140 #define SDIO_CLK_32M 32000000 // 32 MHz
141 #define SDIO_CLK_25M 25000000 // 25 MHz, 2 div for 50MHz
142 #define SDIO_CLK_24M 24000000 // 25 MHz, 2 div for 50MHz
143 #define SDIO_CLK_20M 20000000 // 20 MHz
144 #define SDIO_CLK_16M 16000000 // 16 MHz
145 #define SDIO_CLK_12P5M 12500000 // 12.5 MHz, 4 div for 50MHz
146 #define SDIO_CLK_10M 10000000 // 10 MHz
147 #define SDIO_CLK_8M 8000000 // 8 MHz
148 #define SDIO_CLK_6P25M 6250000 // 6.25 MHz, 8 div for 50MHz
149 #define SDIO_CLK_4M 4000000 // 4 MHz
150 #define SDIO_CLK_3P125M 3125000 // 3.125 MHz, 16 div for 50MHz
151 #define SDIO_CLK_2M 2000000 // 2 MHz
152 #define SDIO_CLK_1P56M 1562500 // 1.562 MHz, 32 div for 50MHz
153 #define SDIO_CLK_1M 1000000 // 1 MHz
154 #define SDIO_CLK_781K 781250 // 781 KHz, 64 div for 50MHz
155 #define SDIO_CLK_390K 390625 // 390 KHz, 128 div for 50MHz
156 #define SDIO_CLK_250K 250000 // 250 KHz
157 #define SDIO_CLK_195K 195312 // 195 KHz, 256 div for 50MHz
158 #define SDIO_CLK_125K 125000 // 125 KHz
160 #define SDIO_BASE_CLK SDIO_BASE_CLK_96M // 96MHz
161 #define SDIO_SD_MAX_CLK SDIO_CLK_48M //SDIO_CLK_50M//
163 #define USB_FIFO_MAX_WORD 16
164 #define USB_FIFO_MAX_BYTE 1024
165 #define USB_MAX_TRANSFER_SIZE (32*1024)
169 //define transfer mode and command mode...
171 #define SDIO_CMD_TYPE_ABORT (3<<22)
172 #define SDIO_CMD_TYPE_RESUME (2<<22)
173 #define SDIO_CMD_TYPE_SUSPEND (1<<22)
174 #define SDIO_CMD_TYPE_NML (0<<22)
176 #define SDIO_CMD_DATA_PRESENT BIT_21
178 #define SDIO_CMD_INDEX_CHK BIT_20
179 #define SDIO_CMD_CRC_CHK BIT_19
180 #define SDIO_CMD_NO_RSP (0x00<<16)
181 #define SDIO_CMD_RSP_136 (0x01<<16)
182 #define SDIO_CMD_RSP_48 (0x02<<16)
183 #define SDIO_CMD_RSP_48_BUSY (0x03<<16)
185 #define SDIO_NO_RSP 0x0;
186 #define SDIO_R1 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
187 #define SDIO_R2 ( SDIO_CMD_RSP_136 | SDIO_CMD_CRC_CHK )
188 #define SDIO_R3 SDIO_CMD_RSP_48
189 #define SDIO_R4 SDIO_CMD_RSP_48
190 #define SDIO_R5 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
191 #define SDIO_R6 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
192 #define SDIO_R7 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
193 #define SDIO_R1B ( SDIO_CMD_RSP_48_BUSY | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
194 #define SDIO_R5B ( SDIO_CMD_RSP_48_BUSY | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
196 #define SDIO_TRANS_COMP_ATA BIT_6
197 #define SDIO_TRANS_MULTIBLK BIT_5
198 #define SDIO_TRANS_DIR_READ BIT_4
199 #define SDIO_TRANS_AUTO_CMD12_EN BIT_2
200 #define SDIO_TRANS_BLK_CNT_EN BIT_1
201 #define SDIO_TRANS_DMA_EN BIT_0
204 //define normal and error sts index...
205 #define SDIO_VENDOR_SPEC_ERR (BIT_29|BIT_30|BIT_31)
206 #define SDIO_TARGET_RESP_ERR (BIT_28)
207 #define SDIO_AUTO_CMD12_ERR (BIT_24)
208 #define SDIO_CURRENT_LMT_ERR (BIT_23)
209 #define SDIO_DATA_ENDBIT_ERR (BIT_22)
210 #define SDIO_DATA_CRC_ERR (BIT_21)
211 #define SDIO_DATA_TMOUT_ERR (BIT_20)
212 #define SDIO_CMD_INDEX_ERR (BIT_19)
213 #define SDIO_CMD_ENDBIT_ERR (BIT_18)
214 #define SDIO_CMD_CRC_ERR (BIT_17)
215 #define SDIO_CMD_TMOUT_ERR (BIT_16)
216 #define SDIO_ERROR_INT (BIT_15)
217 #define SDIO_CARD_INT (BIT_8)
218 #define SDIO_CARD_REMOVAL (BIT_7)
219 #define SDIO_CARD_INSERTION (BIT_6)
220 #define SDIO_BUF_READ_RDY (BIT_5)
221 #define SDIO_BUF_WRITE_RDY (BIT_4)
222 #define SDIO_DMA_INT (BIT_3)
223 #define SDIO_BLK_GAP_EVT (BIT_2)
224 #define SDIO_TRANSFER_CMPLETE (BIT_1)
225 #define SDIO_CMD_CMPLETE (BIT_0)
227 /**----------------------------------------------------------------------------*
228 ** Local Function Prototype **
229 **----------------------------------------------------------------------------*/
231 /**----------------------------------------------------------------------------*
232 ** Function Prototype **
233 **----------------------------------------------------------------------------*/
236 /**----------------------------------------------------------------------------*
238 **----------------------------------------------------------------------------*/
242 /**---------------------------------------------------------------------------*/