4 /* arch/arm/mach-sc8800s/include/mach/regs_global.h
6 * Copyright (C) 2010 Spreadtrum
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <asm/arch/bits.h>
20 /*----------Global Registers----------*/
21 #define GREG_BASE 0x4B000000
23 #define GR_GEN0 (GREG_BASE + 0x0008)
24 #define GR_PCTL (GREG_BASE + 0x000C)
25 #define GR_IRQ (GREG_BASE + 0x0010)
26 #define GR_ICLR (GREG_BASE + 0x0014)
27 #define GR_GEN1 (GREG_BASE + 0x0018)
28 #define GR_GEN3 (GREG_BASE + 0x001C)
29 //#define GR_HWRST (GREG_BASE + 0x0020)
30 #define BOOT_FLAG (GREG_BASE + 0x0020) //It's called GR_HWRST in other chip define
31 #define GR_MPLL_MN (GREG_BASE + 0x0024)
32 #define GR_PIN_CTL (GREG_BASE + 0x0028)
33 #define GR_GEN2 (GREG_BASE + 0x002C)
34 #define GR_ARM_BOOT_ADDR (GREG_BASE + 0x0030)
35 #define GR_STC_STATE (GREG_BASE + 0x0034)
37 #define GR_BUSCLK (GREG_BASE + 0x0044) ////GR_BUSCLK_ALM
38 #define GR_ARCH_CTL (GREG_BASE + 0x0048)
39 #define GR_SOFT_RST (GREG_BASE + 0x004C)
41 #define GR_NFC_MEM_DLY (GREG_BASE + 0x0058)
42 #define GR_CLK_DLY (GREG_BASE + 0x005C)
43 #define GR_GEN4 (GREG_BASE + 0x0060)
45 #define GR_POWCTL0 (GREG_BASE + 0x0068)
46 #define GR_POWCTL1 (GREG_BASE + 0x006C)
47 #define GR_PLL_SCR (GREG_BASE + 0x0070)
48 #define GR_CLK_EN (GREG_BASE + 0x0074)
50 #define GR_CLK_GEN5 (GREG_BASE + 0x007C)
52 #define GR_SWRST GR_SOFT_RST ////mingweiflag GR_SOFT_RST or GR_SWRST?
53 #define GR_BUSCLK_ALM GR_BUSCLK
54 #define LDO_USB_PD BIT_9
59 #define GEN0_TIMER_EN BIT_2
60 #define GEN0_SIM0_EN BIT_3
61 #define GEN0_I2C_EN BIT_4
62 #define GEN0_GPIO_EN BIT_5
63 #define GEN0_ADI_EN BIT_6
64 #define GEN0_EFUSE_EN BIT_7
65 #define GEN0_KPD_EN BIT_8
67 #define GEN0_MCU_DSP_RST BIT_10
68 #define GEN0_MCU_SOFT_RST BIT_11
69 #define GEN0_I2S_EN BIT_12
70 #define GEN0_PIN_EN BIT_13
71 #define GEN0_CCIR_MCLK_EN BIT_14
72 #define GEN0_EPT_EN BIT_15
73 #define GEN0_SIM1_EN BIT_16
74 #define GEN0_SPI_EN BIT_17
76 #define GEN0_SYST_EN BIT_19
77 #define GEN0_UART0_EN BIT_20
78 #define GEN0_UART1_EN BIT_21
79 #define GEN0_UART2_EN BIT_22
80 #define GEN0_VB_EN BIT_23
81 #define GEN0_GPIO_RTC_EN BIT_24
83 #define GEN0_KPD_RTC_EN BIT_26
84 #define GEN0_SYST_RTC_EN BIT_27
85 #define GEN0_TMR_RTC_EN BIT_28
91 #define GEN1_MPLL_MN_EN BIT_9
92 #define GEN1_CLK_AUX0_EN BIT_10
93 #define GEN1_CLK_AUX1_EN BIT_11
95 #define GEN1_RTC_ARCH_EN BIT_18
98 #define MISC0_UART1_MUX_SEL BIT_8
101 the APB Soft Reset register bit
103 #define SWRST_I2C_RST BIT_0
104 #define SWRST_KPD_RST BIT_1
106 #define SWRST_SIM0_RST BIT_5
107 #define SWRST_SIM1_RST BIT_6
109 #define SWRST_TIMER_RST BIT_8
111 #define SWRST_EPT_RST BIT_10
112 #define SWRST_UART0_RST BIT_11
113 #define SWRST_UART1_RST BIT_12
114 #define SWRST_UART2_RST BIT_13
115 #define SWRST_SPI_RST BIT_14
117 #define SWRST_IIS_RST BIT_16
119 #define SWRST_SYST_RST BIT_19
120 #define SWRST_PINREG_RST BIT_20
121 #define SWRST_GPIO_RST BIT_21
122 #define ADI_SOFT_RST BIT_22
123 #define SWRST_VBC_RST BIT_23
124 #define SWRST_PWM0_RST BIT_24
125 #define SWRST_PWM1_RST BIT_25
126 #define SWRST_PWM2_RST BIT_26
127 #define SWRST_PWM3_RST BIT_27
128 #define SWRST_EFUSE_RST BIT_28
132 the ARM VB CTRL register bit
134 #define ARM_VB_IIS_SEL BIT_0
135 #define ARM_VB_MCLKON BIT_1
136 #define ARM_VB_DA0ON BIT_2
137 #define ARM_VB_DA1ON BIT_3
138 #define ARM_VB_AD0ON BIT_4
139 #define ARM_VB_AD1ON BIT_5
140 #define ARM_VB_ANAON BIT_6
141 #define ARM_VB_ACC BIT_7
143 #define ARM_VB_ADCON ARM_VB_AD0ON
147 the Interrupt control register bit
149 #define IRQ_MCU_IRQ0 BIT_0
150 #define IRQ_MCU_FRQ0 BIT_1
151 #define IRQ_MCU_IRQ1 BIT_2
152 #define IRQ_MCU_FRQ1 BIT_3
154 #define IRQ_VBCAD_IRQ BIT_5
155 #define IRQ_VBCDA_IRQ BIT_6
157 #define IRQ_RFT_INT BIT_12
160 the Interrupt clear register bit
162 #define ICLR_DSP_IRQ0_CLR BIT_0
163 #define ICLR_DSP_FRQ0_CLR BIT_1
164 #define ICLR_DSP_IRQ1_CLR BIT_2
165 #define ICLR_DSP_FIQ1_CLR BIT_3
167 #define ICLR_VBCAD_IRQ_CLR BIT_5
168 #define ICLR_VBCDA_IRQ_CLR BIT_6
170 #define ICLR_RFT_INT_CLR BIT_12
174 the Clock enable register bit
177 #define CLK_PWM0_EN BIT_21
178 #define CLK_PWM1_EN BIT_22
179 #define CLK_PWM2_EN BIT_23
180 #define CLK_PWM3_EN BIT_24
181 #define CLK_PWM0_SEL BIT_25
182 #define CLK_PWM1_SEL BIT_26
183 #define CLK_PWM2_SEL BIT_27
184 #define CLK_PWM3_SEL BIT_28
187 #define POWCTL1_CONFIG 0x7FFFF903
189 #endif //_SC8800G_REG_GLOBAL_H_