1 /******************************************************************************
2 ** File Name: cp_mode.c *
3 ** Author: Andrew.Yang *
5 ** Copyright: 2014 Spreatrum, Incoporated. All Rights Reserved. *
6 ** Description: This file defines the logic interfaces called during boot,*
7 ** including reset mode setting, initialization etc.
8 ******************************************************************************
10 ******************************************************************************
12 ** ------------------------------------------------------------------------- *
13 ** DATE NAME DESCRIPTION *
14 ** 31/03/2014 Andrew Create. *
15 ******************************************************************************/
17 /**---------------------------------------------------------------------------*
19 **---------------------------------------------------------------------------*/
20 /**---------------------------------------------------------------------------*
22 **---------------------------------------------------------------------------*/
27 /**---------------------------------------------------------------------------*
29 **---------------------------------------------------------------------------*/
31 #define msleep(cnt) udelay(cnt*1000)
32 /**---------------------------------------------------------------------------*
34 **---------------------------------------------------------------------------*/
36 /**---------------------------------------------------------------------------*
37 ** Local Function Prototypes *
38 **---------------------------------------------------------------------------*/
40 /**---------------------------------------------------------------------------*
41 ** Function Prototypes *
42 **---------------------------------------------------------------------------*/
43 /*****************************************************************************/
44 // Description: Sets the different kinds of reset modes, used in normal p-
45 // ower up mode, watchdog reset mode and calibration mode etc.
46 // Author: Andrew.Yang
48 /*****************************************************************************/
49 static inline void cp0_arm0_boot(void)
53 /* open cp0 pmu controller
54 *((volatile u32*)REG_PMU_APB_PD_CP0_SYS_CFG ) &= ~BIT_25;
56 *((volatile u32*)REG_PMU_APB_PD_CP0_SYS_CFG ) &= ~BIT_28;
59 *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~BIT_17; /*clear cp0 sleep */
60 *((volatile u32*)REG_PMU_APB_CP_SOFT_RST)|= BIT_0; /* reset cp0 */
62 *((volatile u32*)REG_PMU_APB_CP_SOFT_RST) &= ~BIT_0; /* clear cp0 force shutdown */
66 state = *((volatile u32*)REG_PMU_APB_CP_SOFT_RST);
72 /*****************************************************************************/
73 // Description: Gets the current reset mode.
74 // Author: Andrew.Yang
76 /*****************************************************************************/
77 static inline void cp1_boot(void)
80 *((volatile u32*)REG_AON_APB_APB_RST1) |= BIT_20; /* reset cp1 */
82 *((volatile u32*)REG_AON_APB_APB_RST1) &= ~BIT_20; /*clear reset cp1 */
83 #ifdef CONFIG_ARCH_SCX20L
84 *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~(BIT_17 |BIT_18 | BIT_20);/*clear cp0/cp1 sleep*/
86 *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~(BIT_18 | BIT_20); /*clear cp1 sleep */
89 *((volatile u32*)REG_PMU_APB_CP_SOFT_RST)|= BIT_1; /* reset cp0 */
91 *((volatile u32*)REG_PMU_APB_CP_SOFT_RST) &= ~BIT_1; /* clear cp0 force shutdown */
95 state = *((volatile u32*)REG_PMU_APB_CP_SOFT_RST);
100 /*****************************************************************************/
101 // Description: Gets the current reset mode.
102 // Author: Andrew.Yang
104 /*****************************************************************************/
105 static inline void pmic_arm7_RAM_active(void)
108 *((volatile u32*)REG_AON_APB_ARM7_SYS_SOFT_RST) |= BIT_0; /* 0x402e0114*/
110 *((volatile u32*)REG_PMU_APB_CP_SOFT_RST)|= BIT_8; /* reset arm7*/
112 *((volatile u32*)REG_PMU_APB_CP_SOFT_RST) &= ~BIT_8; /* clear arm7*/
115 state = *((volatile u32*)REG_PMU_APB_CP_SOFT_RST);
122 /*****************************************************************************/
123 // Description: Gets the current reset mode.
124 // Author: Andrew.Yang
126 /*****************************************************************************/
127 static inline void pmic_arm7_boot(void)
130 *((volatile u32*)REG_PMU_APB_SLEEP_CTRL) &= ~BIT_21; /*clear arm7 force sleep */
131 *((volatile u32*)REG_AON_APB_ARM7_SYS_SOFT_RST) &= ~BIT_0; /* reset arm7 */
136 /*****************************************************************************/
137 // Description: After normal power on, the HW_RST flag should be reset in
138 // order to judge differrent reset conditions between normal
139 // power on reset and watchdog reset.
140 // Author: Andrew.Yang
142 /*****************************************************************************/
143 static inline void cp2_boot()
147 /*****************************************************************************/
148 // Description: Before watchdog reset, writting HW_RST flag is uesed to j-
149 // udge differrent watchdog reset conditions between MCU reset
150 // and system-halted.
151 // Author: Andrew.Yang
153 /*****************************************************************************/
154 static inline void cp0_arm1_boot(void)
158 static inline void cp0_arm2_boot(void)
163 /**---------------------------------------------------------------------------*
165 **---------------------------------------------------------------------------*/