2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
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4 * This file is dual-licensed: you can use it either under the terms
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5 * of the GPL or the X11 license, at your option. Note that this dual
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6 * licensing only applies to this file, and not this project as a
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11 #ifndef __H_REGS_MM_AHB_RF_HEADFILE_H__
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12 #define __H_REGS_MM_AHB_RF_HEADFILE_H__ __FILE__
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14 #define REGS_MM_AHB_RF
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16 /* registers definitions for MM_AHB_RF */
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17 #define REG_MM_AHB_RF_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)
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18 #define REG_MM_AHB_RF_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)
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19 #define REG_MM_AHB_RF_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)
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20 #define REG_MM_AHB_RF_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)
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21 #define REG_MM_AHB_RF_MM_QOS_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)
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25 /* bits definitions for register REG_MM_AHB_RF_AHB_EB */
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26 #define BIT_MMU_EB ( BIT(7) )
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27 #define BIT_CKG_EB ( BIT(6) )
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28 #define BIT_JPG_EB ( BIT(5) )
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29 #define BIT_CSI_EB ( BIT(4) )
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30 #define BIT_VSP_EB ( BIT(3) )
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31 #define BIT_ISP_EB ( BIT(2) )
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32 #define BIT_CCIR_EB ( BIT(1) )
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33 #define BIT_DCAM_EB ( BIT(0) )
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35 /* bits definitions for register REG_MM_AHB_RF_AHB_RST */
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36 #define BIT_MMU_SOFT_RST ( BIT(14) )
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37 #define BIT_CKG_SOFT_RST ( BIT(13) )
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38 #define BIT_MM_MTX_SOFT_RST ( BIT(12) )
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39 #define BIT_OR1200_SOFT_RST ( BIT(11) )
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40 #define BIT_ROT_SOFT_RST ( BIT(10) )
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41 #define BIT_CAM2_SOFT_RST ( BIT(9) )
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42 #define BIT_CAM1_SOFT_RST ( BIT(8) )
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43 #define BIT_CAM0_SOFT_RST ( BIT(7) )
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44 #define BIT_JPG_SOFT_RST ( BIT(6) )
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45 #define BIT_CSI_SOFT_RST ( BIT(5) )
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46 #define BIT_VSP_SOFT_RST ( BIT(4) )
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47 #define BIT_ISP_CFG_SOFT_RST ( BIT(3) )
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48 #define BIT_ISP_LOG_SOFT_RST ( BIT(2) )
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49 #define BIT_CCIR_SOFT_RST ( BIT(1) )
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50 #define BIT_DCAM_SOFT_RST ( BIT(0) )
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52 /* bits definitions for register REG_MM_AHB_RF_GEN_CKG_CFG */
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53 #define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) )
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54 #define BIT_MM_AXI_CKG_EN ( BIT(7) )
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55 #define BIT_JPG_AXI_CKG_EN ( BIT(6) )
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56 #define BIT_VSP_AXI_CKG_EN ( BIT(5) )
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57 #define BIT_ISP_AXI_CKG_EN ( BIT(4) )
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58 #define BIT_DCAM_AXI_CKG_EN ( BIT(3) )
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59 #define BIT_SENSOR_CKG_EN ( BIT(2) )
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60 #define BIT_MIPI_CSI_CKG_EN ( BIT(1) )
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61 #define BIT_CPHY_CFG_CKG_EN ( BIT(0) )
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63 /* bits definitions for register REG_MM_AHB_RF_MIPI_CSI2_CTRL */
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64 #define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
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65 #define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) )
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66 #define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) )
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67 #define BIT_MIPI_CPHY_SEL ( BIT(0) )
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69 /* bits definitions for register REG_MM_AHB_RF_MM_QOS_CFG */
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70 #define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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71 #define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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72 #define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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73 #define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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74 #define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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75 #define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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76 #define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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77 #define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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