2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 #ifndef __H_REGS_AP_AHB_RF_HEADFILE_H__
12 #define __H_REGS_AP_AHB_RF_HEADFILE_H__ __FILE__
14 #define REGS_AP_AHB_RF
16 /* registers definitions for controller REGS_AP_AHB */
17 #define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)
18 #define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)
19 #define REG_AP_AHB_CA7_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)
20 #define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)
21 #define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)
22 #define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)
23 #define REG_AP_AHB_JMP_ADDR_CA7_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)
24 #define REG_AP_AHB_JMP_ADDR_CA7_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)
25 #define REG_AP_AHB_JMP_ADDR_CA7_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)
26 #define REG_AP_AHB_JMP_ADDR_CA7_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)
27 #define REG_AP_AHB_CA7_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)
28 #define REG_AP_AHB_CA7_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)
29 #define REG_AP_AHB_CA7_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)
30 #define REG_AP_AHB_CA7_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)
31 #define REG_AP_AHB_CA7_CKG_DIV_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0038)
32 #define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x003C)
33 #define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0040)
34 #define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0044)
35 #define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0048)
36 #define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x004C)
37 #define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0050)
38 #define REG_AP_AHB_CA7_CKG_SEL_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0054)
39 #define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)
40 #define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)
41 #define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)
42 #define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)
43 #define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)
44 #define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)
45 #define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)
46 #define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)
47 #define REG_AP_AHB_OTG_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)
48 #define REG_AP_AHB_OTG_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)
49 #define REG_AP_AHB_OTG_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)
50 #define REG_AP_AHB_HSIC_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)
51 #define REG_AP_AHB_HSIC_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)
52 #define REG_AP_AHB_HSIC_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)
53 #define REG_AP_AHB_ZIP_MTX_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)
54 #define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)
56 /* bits definitions for register REG_AP_AHB_AHB_EB */
57 #define BIT_ZIPMTX_EB ( BIT(23) )
58 #define BIT_LVDS_EB ( BIT(22) )
59 #define BIT_ZIPDEC_EB ( BIT(21) )
60 #define BIT_ZIPENC_EB ( BIT(20) )
61 #define BIT_NANDC_ECC_EB ( BIT(19) )
62 #define BIT_NANDC_2X_EB ( BIT(18) )
63 #define BIT_NANDC_EB ( BIT(17) )
64 #define BIT_BUSMON2_EB ( BIT(16) )
65 #define BIT_BUSMON1_EB ( BIT(15) )
66 #define BIT_BUSMON0_EB ( BIT(14) )
67 #define BIT_SPINLOCK_EB ( BIT(13) )
68 #define BIT_EMMC_EB ( BIT(11) )
69 #define BIT_SDIO2_EB ( BIT(10) )
70 #define BIT_SDIO1_EB ( BIT(9) )
71 #define BIT_SDIO0_EB ( BIT(8) )
72 #define BIT_DRM_EB ( BIT(7) )
73 #define BIT_NFC_EB ( BIT(6) )
74 #define BIT_DMA_EB ( BIT(5) )
75 #define BIT_OTG_EB ( BIT(4) )
76 #define BIT_GSP_EB ( BIT(3) )
77 #define BIT_HSIC_EB ( BIT(2) )
78 #define BIT_DISPC_EB ( BIT(1) )
79 #define BIT_DSI_EB ( BIT(0) )
81 /* bits definitions for register REG_AP_AHB_AHB_RST */
82 #define BIT_HSIC_PHY_SOFT_RST ( BIT(30) )
83 #define BIT_HSIC_UTMI_SOFT_RST ( BIT(29) )
84 #define BIT_HSIC_SOFT_RST ( BIT(28) )
85 #define BIT_LVDS_SOFT_RST ( BIT(25) )
86 #define BIT_ZIP_MTX_SOFT_RST ( BIT(24) )
87 #define BIT_ZIPDEC_SOFT_RST ( BIT(23) )
88 #define BIT_ZIPENC_SOFT_RST ( BIT(22) )
89 #define BIT_NANDC_SOFT_RST ( BIT(20) )
90 #define BIT_BUSMON2_SOFT_RST ( BIT(19) )
91 #define BIT_BUSMON1_SOFT_RST ( BIT(18) )
92 #define BIT_BUSMON0_SOFT_RST ( BIT(17) )
93 #define BIT_SPINLOCK_SOFT_RST ( BIT(16) )
94 #define BIT_EMMC_SOFT_RST ( BIT(14) )
95 #define BIT_SDIO2_SOFT_RST ( BIT(13) )
96 #define BIT_SDIO1_SOFT_RST ( BIT(12) )
97 #define BIT_SDIO0_SOFT_RST ( BIT(11) )
98 #define BIT_DRM_SOFT_RST ( BIT(10) )
99 #define BIT_NFC_SOFT_RST ( BIT(9) )
100 #define BIT_DMA_SOFT_RST ( BIT(8) )
101 #define BIT_OTG_PHY_SOFT_RST ( BIT(6) )
102 #define BIT_OTG_UTMI_SOFT_RST ( BIT(5) )
103 #define BIT_OTG_SOFT_RST ( BIT(4) )
104 #define BIT_GSP_SOFT_RST ( BIT(3) )
105 #define BIT_DISP_MTX_SOFT_RST ( BIT(2) )
106 #define BIT_DISPC_SOFT_RST ( BIT(1) )
107 #define BIT_DSI_SOFT_RST ( BIT(0) )
109 /* bits definitions for register REG_AP_AHB_CA7_RST_SET */
110 #define BIT_CA7_CS_DBG_SOFT_RST ( BIT(14) )
111 #define BIT_CA7_L2_SOFT_RST ( BIT(13) )
112 #define BIT_CA7_SOCDBG_SOFT_RST ( BIT(12) )
113 #define BITS_CA7_ETM_SOFT_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
114 #define BITS_CA7_DBG_SOFT_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
115 #define BITS_CA7_CORE_SOFT_RST(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
117 /* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */
118 #define BIT_CA7_C3_AUTO_SLP_EN ( BIT(15) )
119 #define BIT_CA7_C2_AUTO_SLP_EN ( BIT(14) )
120 #define BIT_CA7_C1_AUTO_SLP_EN ( BIT(13) )
121 #define BIT_CA7_C0_AUTO_SLP_EN ( BIT(12) )
122 #define BIT_CA7_C3_WFI_SHUTDOWN_EN ( BIT(11) )
123 #define BIT_CA7_C2_WFI_SHUTDOWN_EN ( BIT(10) )
124 #define BIT_CA7_C1_WFI_SHUTDOWN_EN ( BIT(9) )
125 #define BIT_CA7_C0_WFI_SHUTDOWN_EN ( BIT(8) )
126 #define BIT_MCU_CA7_C3_SLEEP ( BIT(7) )
127 #define BIT_MCU_CA7_C2_SLEEP ( BIT(6) )
128 #define BIT_MCU_CA7_C1_SLEEP ( BIT(5) )
129 #define BIT_MCU_CA7_C0_SLEEP ( BIT(4) )
130 #define BIT_AP_PERI_FORCE_ON ( BIT(2) )
131 #define BIT_AP_PERI_FORCE_SLP ( BIT(1) )
132 #define BIT_AP_APB_SLEEP ( BIT(0) )
134 /* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */
135 #define BIT_GSP_CKG_FORCE_EN ( BIT(9) )
136 #define BIT_GSP_AUTO_GATE_EN ( BIT(8) )
137 #define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) )
138 #define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) )
139 #define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(3) )
140 #define BIT_CA7_DBG_FORCE_SLEEP ( BIT(2) )
141 #define BIT_CA7_DBG_AUTO_GATE_EN ( BIT(1) )
142 #define BIT_CA7_CORE_AUTO_GATE_EN ( BIT(0) )
144 /* bits definitions for register REG_AP_AHB_HOLDING_PEN */
145 #define BITS_HOLDING_PEN(_x_) ( (_x_) << 0 )
147 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */
148 #define BITS_JMP_ADDR_CA7_C0(_x_) ( (_x_) << 0 )
150 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */
151 #define BITS_JMP_ADDR_CA7_C1(_x_) ( (_x_) << 0 )
153 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */
154 #define BITS_JMP_ADDR_CA7_C2(_x_) ( (_x_) << 0 )
156 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */
157 #define BITS_JMP_ADDR_CA7_C3(_x_) ( (_x_) << 0 )
159 /* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */
160 #define BIT_CA7_C0_PU_LOCK ( BIT(0) )
162 /* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */
163 #define BIT_CA7_C1_PU_LOCK ( BIT(0) )
165 /* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */
166 #define BIT_CA7_C2_PU_LOCK ( BIT(0) )
168 /* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */
169 #define BIT_CA7_C3_PU_LOCK ( BIT(0) )
171 /* bits definitions for register REG_AP_AHB_CA7_CKG_DIV_CFG */
172 #define BITS_CA7_DBG_CKG_DIV(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)) )
173 #define BITS_CA7_AXI_CKG_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
174 #define BITS_CA7_MCU_CKG_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
176 /* bits definitions for register REG_AP_AHB_MCU_PAUSE */
177 #define BIT_DMA_ACT_LIGHT_EN ( BIT(5) )
178 #define BIT_MCU_SLEEP_FOLLOW_CA7_EN ( BIT(4) )
179 #define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) )
180 #define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) )
181 #define BIT_MCU_SYS_SLEEP_EN ( BIT(1) )
182 #define BIT_MCU_CORE_SLEEP ( BIT(0) )
184 /* bits definitions for register REG_AP_AHB_MISC_CKG_EN */
185 #define BIT_ASHB_CA7_DBG_VLD ( BIT(9) )
186 #define BIT_ASHB_CA7_DBG_EN ( BIT(8) )
187 #define BIT_DISP_TMC_CKG_EN ( BIT(4) )
188 #define BIT_DPHY_REF_CKG_EN ( BIT(1) )
189 #define BIT_DPHY_CFG_CKG_EN ( BIT(0) )
191 /* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */
192 #define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
194 /* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */
195 #define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
197 /* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */
198 #define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
200 /* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */
201 #define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
203 /* bits definitions for register REG_AP_AHB_CA7_CKG_SEL_CFG */
204 #define BITS_CA7_MCU_CKG_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
206 /* bits definitions for register REG_AP_AHB_MISC_CFG */
207 #define BITS_EMMC_SLOT_SEL(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) )
208 #define BITS_SDIO0_SLOT_SEL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
209 #define BITS_BUSMON2_CHN_SEL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
210 #define BITS_BUSMON1_CHN_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
211 #define BITS_BUSMON0_CHN_SEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
212 #define BITS_SDIO2_SLOT_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
213 #define BITS_SDIO1_SLOT_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
215 /* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */
216 #define BITS_HPROT_NFC(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
217 #define BITS_HPROT_EMMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
218 #define BITS_HPROT_SDIO2(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
219 #define BITS_HPROT_SDIO1(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
220 #define BITS_HPROT_SDIO0(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
221 #define BITS_HPROT_DMAW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
222 #define BITS_HPROT_DMAR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
224 /* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */
225 #define BIT_CA7_STANDBYWFIL2 ( BIT(12) )
226 #define BITS_CA7_ETMSTANDBYWFX(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
227 #define BITS_CA7_STANDBYWFE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
228 #define BITS_CA7_STANDBYWFI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
230 /* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */
231 #define BITS_CLK_NANDC_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) )
232 #define BITS_CLK_NANDC2X_DIV(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
233 #define BITS_CLK_NANDC2X_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
235 /* bits definitions for register REG_AP_AHB_LVDS_CFG */
236 #define BITS_LVDS_TXCLKDATA(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
237 #define BITS_LVDS_TXCOM(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
238 #define BITS_LVDS_TXSLEW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
239 #define BITS_LVDS_TXSW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
240 #define BITS_LVDS_TXRERSER(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
241 #define BITS_LVDS_PRE_EMP(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) )
242 #define BIT_LVDS_TXPD ( BIT(0) )
244 /* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */
245 #define BIT_LVDS_PLL_LOCK_DET ( BIT(31) )
246 #define BITS_LVDS_PLL_REFIN(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)) )
247 #define BITS_LVDS_PLL_LPF(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
248 #define BIT_LVDS_PLL_DIV_S ( BIT(18) )
249 #define BITS_LVDS_PLL_IBIAS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
250 #define BITS_LVDS_PLLN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
252 /* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */
253 #define BITS_LVDS_PLL_KINT(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
254 #define BITS_LVDS_PLL_RSV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
255 #define BIT_LVDS_PLL_MOD_EN ( BIT(7) )
256 #define BIT_LVDS_PLL_SDM_EN ( BIT(6) )
257 #define BITS_LVDS_PLL_NINT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
259 /* bits definitions for register REG_AP_AHB_AP_QOS_CFG */
260 #define BITS_QOS_R_TMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
261 #define BITS_QOS_W_TMC(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
262 #define BITS_QOS_R_DISPC(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
263 #define BITS_QOS_W_DISPC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
265 /* bits definitions for register REG_AP_AHB_OTG_PHY_TUNE */
266 #define BIT_OTG_TXPREEMPPULSETUNE ( BIT(20) )
267 #define BITS_OTG_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) )
268 #define BITS_OTG_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
269 #define BITS_OTG_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
270 #define BITS_OTG_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
271 #define BITS_OTG_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
272 #define BITS_OTG_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
273 #define BITS_OTG_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
275 /* bits definitions for register REG_AP_AHB_OTG_PHY_TEST */
276 #define BIT_OTG_ATERESET ( BIT(31) )
277 #define BIT_OTG_VBUS_VALID_EXT_SEL ( BIT(26) )
278 #define BIT_OTG_VBUS_VALID_EXT ( BIT(25) )
279 #define BIT_OTG_OTGDISABLE ( BIT(24) )
280 #define BIT_OTG_TESTBURNIN ( BIT(21) )
281 #define BIT_OTG_LOOPBACKENB ( BIT(20) )
282 #define BITS_OTG_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
283 #define BITS_OTG_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
284 #define BIT_OTG_TESTCLK ( BIT(13) )
285 #define BIT_OTG_TESTDATAOUTSEL ( BIT(12) )
286 #define BITS_OTG_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
287 #define BITS_OTG_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
289 /* bits definitions for register REG_AP_AHB_OTG_PHY_CTRL */
290 #define BITS_OTG_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) )
291 #define BIT_OTG_TXBITSTUFFENH ( BIT(23) )
292 #define BIT_OTG_TXBITSTUFFEN ( BIT(22) )
293 #define BIT_OTG_DMPULLDOWN ( BIT(21) )
294 #define BIT_OTG_DPPULLDOWN ( BIT(20) )
295 #define BIT_OTG_DMPULLUP ( BIT(9) )
296 #define BIT_OTG_COMMONONN ( BIT(8) )
297 #define BITS_OTG_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
298 #define BITS_OTG_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
300 /* bits definitions for register REG_AP_AHB_HSIC_PHY_TUNE */
301 #define BITS_HSIC_REFCLK_DIV(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
302 #define BIT_HSIC_TXPREEMPPULSETUNE ( BIT(20) )
303 #define BITS_HSIC_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) )
304 #define BITS_HSIC_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
305 #define BITS_HSIC_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
306 #define BITS_HSIC_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
307 #define BITS_HSIC_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
308 #define BITS_HSIC_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
309 #define BITS_HSIC_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
311 /* bits definitions for register REG_AP_AHB_HSIC_PHY_TEST */
312 #define BIT_HSIC_ATERESET ( BIT(31) )
313 #define BIT_HSIC_VBUS_VALID_EXT_SEL ( BIT(26) )
314 #define BIT_HSIC_VBUS_VALID_EXT ( BIT(25) )
315 #define BIT_HSIC_OTGDISABLE ( BIT(24) )
316 #define BIT_HSIC_TESTBURNIN ( BIT(21) )
317 #define BIT_HSIC_LOOPBACKENB ( BIT(20) )
318 #define BITS_HSIC_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
319 #define BITS_HSIC_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
320 #define BIT_HSIC_TESTCLK ( BIT(13) )
321 #define BIT_HSIC_TESTDATAOUTSEL ( BIT(12) )
322 #define BITS_HSIC_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
323 #define BITS_HSIC_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
325 /* bits definitions for register REG_AP_AHB_HSIC_PHY_CTRL */
326 #define BITS_HSIC_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) )
327 #define BIT_HSIC_TXBITSTUFFENH ( BIT(23) )
328 #define BIT_HSIC_TXBITSTUFFEN ( BIT(22) )
329 #define BIT_HSIC_DMPULLDOWN ( BIT(21) )
330 #define BIT_HSIC_DPPULLDOWN ( BIT(20) )
331 #define BIT_HSIC_IF_MODE ( BIT(16) )
332 #define BIT_IF_SELECT_HSIC ( BIT(13) )
333 #define BIT_HSIC_DBNCE_FLTR_BYPASS ( BIT(12) )
334 #define BIT_HSIC_DMPULLUP ( BIT(9) )
335 #define BIT_HSIC_COMMONONN ( BIT(8) )
336 #define BITS_HSIC_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
337 #define BITS_HSIC_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
339 /* bits definitions for register REG_AP_AHB_ZIP_MTX_QOS_CFG */
340 #define BITS_ZIPMTX_S0_ARQOS(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
341 #define BITS_ZIPMTX_S0_AWQOS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
342 #define BITS_ZIPDEC_ARQOS(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
343 #define BITS_ZIPDEC_AWQOS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
344 #define BITS_ZIPENC_ARQOS(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
345 #define BITS_ZIPENC_AWQOS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
347 /* bits definitions for register REG_AP_AHB_CHIP_ID */
348 #define BITS_CHIP_ID(_x_) ( (_x_) << 0 )
350 /* vars definitions for controller REGS_AP_AHB */
352 #endif /* __REGS_AP_AHB_H__ */