1 /* * Copyright (C) 2012 Spreadtrum Communications Inc.
3 * This software is licensed under the terms of the GNU General Public
4 * License version 2, as published by the Free Software Foundation, and
5 * may be copied, distributed, and modified under those terms.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
17 void sci_adi_init(void);
20 * sci_get_adie_chip_id - read a-die chip id
22 u32 sci_get_adie_chip_id(void);
24 int sci_adi_read(u32 reg);
27 * WARN: the arguments (reg, value) is different from
28 * the general __raw_writel(value, reg)
29 * For sci_adi_write_fast: if set sync 1, then this function will
30 * return until the val have reached hardware.otherwise, just
31 * async write(is maybe in software buffer)
33 int sci_adi_write_fast(u32 reg, u16 val, u32 sync);
34 int sci_adi_write(u32 reg, u16 or_val, u16 clear_msk);
36 static inline int sci_adi_raw_write(u32 reg, u16 val)
38 #if defined(CONFIG_FPGA)
41 return sci_adi_write_fast(reg, val, 1);
42 #endif /* CONFIG_FPGA */
45 static inline int sci_adi_set(u32 reg, u16 bits)
47 #if defined(CONFIG_FPGA)
50 return sci_adi_write(reg, bits, 0);
51 #endif /* CONFIG_FPGA */
54 static inline int sci_adi_clr(u32 reg, u16 bits)
56 #if defined(CONFIG_FPGA)
59 return sci_adi_write(reg, 0, bits);
60 #endif /* CONFIG_FPGA */