1 /******************************************************************************
2 ** File Name: umctl2_reg.h *
5 ** Copyright: 2010 Spreatrum, Incoporated. All Rights Reserved. *
6 ** Description: Refer to uMCTL2 databook for detail *
7 ******************************************************************************
9 ******************************************************************************
11 ** ------------------------------------------------------------------------- *
12 ** DATE NAME DESCRIPTION *
13 ** 01/06/2013 changde.li Create. *
14 ******************************************************************************/
16 #ifndef _UMCTL2_REG_H_
17 #define _UMCTL2_REG_H_
18 /*----------------------------------------------------------------------------*
20 **------------------------------------------------------------------------- */
21 #include "sci_types.h"
23 /**---------------------------------------------------------------------------*
25 **--------------------------------------------------------------------------*/
31 /**---------------------------------------------------------------------------*
33 **---------------------------------------------------------------------------*/
34 /**---------------------------------------------------------------------------*
36 **---------------------------------------------------------------------------*/
37 #define UMCTL_REG_BASE (0x30000000)
38 #define PUBL_REG_BASE (0x30010000)
40 #define UMCTL2_REG_(x) (UMCTL_REG_BASE+(x))
43 *uMCTL2 DDRC registers
45 #define UMCTL_MSTR UMCTL2_REG_(0x0000) /*master*/
46 #define UMCTL_STAT UMCTL2_REG_(0x0004) /*oeration mode status*/
47 #define UMCTL_MRCTRL0 UMCTL2_REG_(0x0010)/*mode register read/werite control*/
48 #define UMCTL_MRCTRL1 UMCTL2_REG_(0x0014)
49 #define UMCTL_MRSTAT UMCTL2_REG_(0x0018)/*mode register read/weite status*/
51 #define UMCTL_DERATEEN UMCTL2_REG_(0x0020)/*temperature derate enable*/
52 #define UMCTL_DERATEINT UMCTL2_REG_(0x0024)/*temperature derate interval*/
53 #define UMCTL_PWRCTL UMCTL2_REG_(0x0030)/*low power control*/
54 #define UMCTL_PWRTMG UMCTL2_REG_(0x0034)/*low power timing*/
55 #define UMCTL_HWLPCTL UMCTL2_REG_(0x0038)/*low power timing*/
58 #define UMCTL_RFSHCTL0 UMCTL2_REG_(0x0050)/*refresh control0*/
59 #define UMCTL_RFSHCTL1 UMCTL2_REG_(0x0054)
60 #define UMCTL_RFSHCTL2 UMCTL2_REG_(0x0058)
61 #define UMCTL_RFSHCTL3 UMCTL2_REG_(0x0060)
62 #define UMCTL_RFSHTMG UMCTL2_REG_(0x0064)/*refresh Timing*/
63 #define UMCTL_ECCCFG0 UMCTL2_REG_(0x0070)/*ecc configuration*/
64 #define UMCTL_ECCCFG1 UMCTL2_REG_(0x0074)
65 #define UMCTL_ECCSTAT UMCTL2_REG_(0x0078)/*ecc status*/
66 #define UMCTL_ECCCLR UMCTL2_REG_(0x007C)/*ecc clear*/
67 #define UMCTL_ECCERRCNT UMCTL2_REG_(0x0080)/*ecc error counter*/
69 #define UMCTL_ECCADDR0 UMCTL2_REG_(0x0084)/*ecc corrected error address reg0*/
70 #define UMCTL_ECCADDR1 UMCTL2_REG_(0x0088)
71 #define UMCTL_ECCSYN0 UMCTL2_REG_(0x008C)/*ecc corected syndrome reg0*/
72 #define UMCTL_ECCSYN1 UMCTL2_REG_(0x0090)
73 #define UMCTL_ECCSYN2 UMCTL2_REG_(0x0094)
74 #define UMCTL_ECCBITMASK0 UMCTL2_REG_(0x0098)
75 #define UMCTL_ECCBITMASK1 UMCTL2_REG_(0x009C)
76 #define UMCTL_ECCBITMASK2 UMCTL2_REG_(0x00A0)
77 #define UMCTL_ECCUADDR0 UMCTL2_REG_(0x00A4)/*ecc uncorrected error address reg0*/
78 #define UMCTL_ECCUADDR1 UMCTL2_REG_(0x00A8)
79 #define UMCTL_ECCUSYN0 UMCTL2_REG_(0x00AC)/*ecc UNcorected syndrome reg0*/
80 #define UMCTL_ECCUSYN1 UMCTL2_REG_(0x00B0)
81 #define UMCTL_ECCUSYN2 UMCTL2_REG_(0x00B4)
82 #define UMCTL_ECCPOISONADDR0 UMCTL2_REG_(0x00B8)/*ecc data poisoning address reg0*/
83 #define UMCTL_ECCPOISONADDR1 UMCTL2_REG_(0x00BC)
86 #define UMCTL_PARCTL UMCTL2_REG_(0x00C0)/*parity control register*/
87 #define UMCTL_PARSTAT UMCTL2_REG_(0x00C4)/*parity status register*/
89 #define UMCTL_INIT0 UMCTL2_REG_(0x00D0)/*SDRAM initialization register0*/
90 #define UMCTL_INIT1 UMCTL2_REG_(0x00D4)
91 #define UMCTL_INIT2 UMCTL2_REG_(0x00D8)
92 #define UMCTL_INIT3 UMCTL2_REG_(0x00DC)
93 #define UMCTL_INIT4 UMCTL2_REG_(0x00E0)
94 #define UMCTL_INIT5 UMCTL2_REG_(0x00E4)
97 #define UMCTL_DIMMCTL UMCTL2_REG_(0x00F0)/*DIMM control register*/
98 #define UMCTL_RANKCTL UMCTL2_REG_(0x00F4)
100 #define UMCTL_DRAMTMG0 UMCTL2_REG_(0x0100)/*SDRAM timing register0*/
101 #define UMCTL_DRAMTMG1 UMCTL2_REG_(0x0104)
102 #define UMCTL_DRAMTMG2 UMCTL2_REG_(0x0108)
103 #define UMCTL_DRAMTMG3 UMCTL2_REG_(0x010C)
104 #define UMCTL_DRAMTMG4 UMCTL2_REG_(0x0110)
105 #define UMCTL_DRAMTMG5 UMCTL2_REG_(0x0114)
106 #define UMCTL_DRAMTMG6 UMCTL2_REG_(0x0118)
107 #define UMCTL_DRAMTMG7 UMCTL2_REG_(0x011C)
108 #define UMCTL_DRAMTMG8 UMCTL2_REG_(0x0120)
110 #define UMCTL_ZQCTL0 UMCTL2_REG_(0x0180)/*ZQ control register0*/
111 #define UMCTL_ZQCTL1 UMCTL2_REG_(0x0184)
112 #define UMCTL_ZQCTL2 UMCTL2_REG_(0x0188)
113 #define UMCTL_ZQSTAT UMCTL2_REG_(0x018C)
116 #define UMCTL_DFITMG0 UMCTL2_REG_(0x0190)/*DFI timing register0*/
117 #define UMCTL_DFITMG1 UMCTL2_REG_(0x0194)
119 #define UMCTL_DFILPCFG0 UMCTL2_REG_(0x0198)/*DFI low power configuration*/
120 #define UMCTL_DFIUPD0 UMCTL2_REG_(0x01A0)/*DFI update register0*/
121 #define UMCTL_DFIUPD1 UMCTL2_REG_(0x01A4)
122 #define UMCTL_DFIUPD2 UMCTL2_REG_(0x01A8)
123 #define UMCTL_DFIUPD3 UMCTL2_REG_(0x01AC)
125 #define UMCTL_DFIMISC UMCTL2_REG_(0x01B0)
127 #define UMCTL_TRAINCTL0 UMCTL2_REG_(0x01D0)/*PHY eval training control reg0*/
128 #define UMCTL_TRAINCTL1 UMCTL2_REG_(0x01D4)
129 #define UMCTL_TRAINCTL2 UMCTL2_REG_(0x01D8)
130 #define UMCTL_TRAINSTAT UMCTL2_REG_(0x01DC)
132 #define UMCTL_ADDRMAP0 UMCTL2_REG_(0x0200)/*address map register0*/
133 #define UMCTL_ADDRMAP1 UMCTL2_REG_(0x0204)
134 #define UMCTL_ADDRMAP2 UMCTL2_REG_(0x0208)
135 #define UMCTL_ADDRMAP3 UMCTL2_REG_(0x020C)
136 #define UMCTL_ADDRMAP4 UMCTL2_REG_(0x0210)
137 #define UMCTL_ADDRMAP5 UMCTL2_REG_(0x0214)
138 #define UMCTL_ADDRMAP6 UMCTL2_REG_(0x0218)
140 #define UMCTL_ODTCFG UMCTL2_REG_(0x0240)/*ODT configuration register*/
141 #define UMCTL_ODTMAP UMCTL2_REG_(0x0244)
143 #define UMCTL_SCHED UMCTL2_REG_(0x0250)/*scheduler control register*/
144 #define UMCTL_PERFHPR0 UMCTL2_REG_(0x0258)/*high priority read CAM reg0*/
145 #define UMCTL_PERFHPR1 UMCTL2_REG_(0x025C)
146 #define UMCTL_PERFLPR0 UMCTL2_REG_(0x0260)
147 #define UMCTL_PERFLPR1 UMCTL2_REG_(0x0264)
149 #define UMCTL_PERFWR0 UMCTL2_REG_(0x0268)/*write CAM reg0*/
150 #define UMCTL_PERFWR1 UMCTL2_REG_(0x026C)
151 #define UMCTL_DBG0 UMCTL2_REG_(0x0300)/*debug register0*/
152 #define UMCTL_DBG1 UMCTL2_REG_(0x0304)
153 #define UMCTL_DBGCAM UMCTL2_REG_(0x0308)/*cam debug register*/
157 *uMCTL2 Multi-Port registers
159 #define UMCTL_PCCFG UMCTL2_REG_(0x0400)/*port common configuration*/
161 #define UMCTL_PCFGR_0 UMCTL2_REG_(0x0404+(0x00)*0xB0)/*Port n configuration read reg*/
162 #define UMCTL_PCFGR_1 UMCTL2_REG_(0x0404+(0x01)*0xB0)
163 #define UMCTL_PCFGR_2 UMCTL2_REG_(0x0404+(0x02)*0xB0)
164 #define UMCTL_PCFGR_3 UMCTL2_REG_(0x0404+(0x03)*0xB0)
165 #define UMCTL_PCFGR_4 UMCTL2_REG_(0x0404+(0x04)*0xB0)
166 #define UMCTL_PCFGR_5 UMCTL2_REG_(0x0404+(0x05)*0xB0)
167 #define UMCTL_PCFGR_6 UMCTL2_REG_(0x0404+(0x06)*0xB0)
168 #define UMCTL_PCFGR_7 UMCTL2_REG_(0x0404+(0x07)*0xB0)
169 #define UMCTL_PCFGR_8 UMCTL2_REG_(0x0404+(0x08)*0xB0)
170 #define UMCTL_PCFGR_9 UMCTL2_REG_(0x0404+(0x09)*0xB0)
171 #define UMCTL_PCFGR_10 UMCTL2_REG_(0x0404+(0x0A)*0xB0)
172 #define UMCTL_PCFGR_11 UMCTL2_REG_(0x0404+(0x0B)*0xB0)
173 #define UMCTL_PCFGR_12 UMCTL2_REG_(0x0404+(0x0C)*0xB0)
174 #define UMCTL_PCFGR_13 UMCTL2_REG_(0x0404+(0x0D)*0xB0)
175 #define UMCTL_PCFGR_14 UMCTL2_REG_(0x0404+(0x0E)*0xB0)
176 #define UMCTL_PCFGR_15 UMCTL2_REG_(0x0404+(0x0F)*0xB0)
179 #define UMCTL_PCFGW_0 UMCTL2_REG_(0x0408+(0x00)*0xB0)/*Port n configuration write reg*/
180 #define UMCTL_PCFGW_1 UMCTL2_REG_(0x0408+(0x01)*0xB0)
181 #define UMCTL_PCFGW_2 UMCTL2_REG_(0x0408+(0x02)*0xB0)
182 #define UMCTL_PCFGW_3 UMCTL2_REG_(0x0408+(0x03)*0xB0)
183 #define UMCTL_PCFGW_4 UMCTL2_REG_(0x0408+(0x04)*0xB0)
184 #define UMCTL_PCFGW_5 UMCTL2_REG_(0x0408+(0x05)*0xB0)
185 #define UMCTL_PCFGW_6 UMCTL2_REG_(0x0408+(0x06)*0xB0)
186 #define UMCTL_PCFGW_7 UMCTL2_REG_(0x0408+(0x07)*0xB0)
187 #define UMCTL_PCFGW_8 UMCTL2_REG_(0x0408+(0x08)*0xB0)
188 #define UMCTL_PCFGW_9 UMCTL2_REG_(0x0408+(0x09)*0xB0)
189 #define UMCTL_PCFGW_10 UMCTL2_REG_(0x0408+(0x0A)*0xB0)
190 #define UMCTL_PCFGW_11 UMCTL2_REG_(0x0408+(0x0B)*0xB0)
191 #define UMCTL_PCFGW_12 UMCTL2_REG_(0x0408+(0x0C)*0xB0)
192 #define UMCTL_PCFGW_13 UMCTL2_REG_(0x0408+(0x0D)*0xB0)
193 #define UMCTL_PCFGW_14 UMCTL2_REG_(0x0408+(0x0E)*0xB0)
194 #define UMCTL_PCFGW_15 UMCTL2_REG_(0x0408+(0x0F)*0xB0)
197 #define UMCTL_PORT_EN_0 UMCTL2_REG_(0x0490+(0x00)*0xB0)/*Port n enable reg*/
198 #define UMCTL_PORT_EN_1 UMCTL2_REG_(0x0490+(0x01)*0xB0)/*Port n enable reg*/
199 #define UMCTL_PORT_EN_2 UMCTL2_REG_(0x0490+(0x02)*0xB0)/*Port n enable reg*/
200 #define UMCTL_PORT_EN_3 UMCTL2_REG_(0x0490+(0x03)*0xB0)/*Port n enable reg*/
201 #define UMCTL_PORT_EN_4 UMCTL2_REG_(0x0490+(0x04)*0xB0)/*Port n enable reg*/
202 #define UMCTL_PORT_EN_5 UMCTL2_REG_(0x0490+(0x05)*0xB0)/*Port n enable reg*/
203 #define UMCTL_PORT_EN_6 UMCTL2_REG_(0x0490+(0x06)*0xB0)/*Port n enable reg*/
204 #define UMCTL_PORT_EN_7 UMCTL2_REG_(0x0490+(0x07)*0xB0)/*Port n enable reg*/
205 #define UMCTL_PORT_EN_8 UMCTL2_REG_(0x0490+(0x08)*0xB0)/*Port n enable reg*/
206 #define UMCTL_PORT_EN_9 UMCTL2_REG_(0x0490+(0x09)*0xB0)/*Port n enable reg*/
210 #define UMCTL2_PCFGIDMASKCH_m_N
211 #define UMCTL2_PCFGIDVALUECH_m_N
216 *Refer to PUBL databook 1.44a for detail,Chapter3.3 Registers.
218 #define PUBL_RIDR (PUBL_REG_BASE+0x00*4) // R - Revision Identification Register
219 #define PUBL_PIR (PUBL_REG_BASE+0x01*4) // R/W - PHY Initialization Register
220 #define PUBL_PGCR (PUBL_REG_BASE+0x02*4) // R/W - PHY General Configuration Register
221 #define PUBL_PGSR (PUBL_REG_BASE+0x03*4) // R - PHY General Status Register
222 #define PUBL_DLLGCR (PUBL_REG_BASE+0x04*4) // R/W - DLL General Control Register
223 #define PUBL_ACDLLCR (PUBL_REG_BASE+0x05*4) // R/W - AC DLL Control Register
224 #define PUBL_PTR0 (PUBL_REG_BASE+0x06*4) // R/W - PHY Timing Register 0
225 #define PUBL_PTR1 (PUBL_REG_BASE+0x07*4) // R/W - PHY Timing Register 1
226 #define PUBL_PTR2 (PUBL_REG_BASE+0x08*4) // R/W - PHY Timing Register 2
227 #define PUBL_ACIOCR (PUBL_REG_BASE+0x09*4) // R/W - AC I/O Configuration Register
228 #define PUBL_DXCCR (PUBL_REG_BASE+0x0A*4) // R/W - DATX8 I/O Configuration Register
229 #define PUBL_DSGCR (PUBL_REG_BASE+0x0B*4) // R/W - DFI Configuration Register
230 #define PUBL_DCR (PUBL_REG_BASE+0x0C*4) // R/W - DRAM Configuration Register
231 #define PUBL_DTPR0 (PUBL_REG_BASE+0x0D*4) // R/W - SDRAM Timing Parameters Register 0
232 #define PUBL_DTPR1 (PUBL_REG_BASE+0x0E*4) // R/W - SDRAM Timing Parameters Register 1
233 #define PUBL_DTPR2 (PUBL_REG_BASE+0x0F*4) // R/W - SDRAM Timing Parameters Register 2
234 #define PUBL_MR0 (PUBL_REG_BASE+0x10*4) // R/W - Mode Register
235 #define PUBL_MR1 (PUBL_REG_BASE+0x11*4) // R/W - Ext}ed Mode Register
236 #define PUBL_MR2 (PUBL_REG_BASE+0x12*4) // R/W - Ext}ed Mode Register 2
237 #define PUBL_MR3 (PUBL_REG_BASE+0x13*4) // R/W - Ext}ed Mode Register 3
238 #define PUBL_ODTCR (PUBL_REG_BASE+0x14*4) // R/W - ODT Configuration Register
239 #define PUBL_DTAR (PUBL_REG_BASE+0x15*4) // R/W - Data Training Address Register
240 #define PUBL_DTDR0 (PUBL_REG_BASE+0x16*4) // R/W - Data Training Data Register 0
241 #define PUBL_DTDR1 (PUBL_REG_BASE+0x17*4) // R/W - Data Training Data Register 1
242 #define PUBL_DCUAR (PUBL_REG_BASE+0X30*4) // R/W - DCU Address Resiter
243 #define PUBL_DCUDR (PUBL_REG_BASE+0x31*4) // R/W - DCU Data Register
244 #define PUBL_DCURR (PUBL_REG_BASE+0x32*4) // R/W - DCU Run Register
245 #define PUBL_DCULR (PUBL_REG_BASE+0x33*4) // R/W - DCU Loop Register
246 #define PUBL_DCUGCR (PUBL_REG_BASE+0x34*4) // R/W - DCU General Configuration Register
247 #define PUBL_DCUTPR (PUBL_REG_BASE+0x35*4) // R/W - DCU Timing Parameters Registers
248 #define PUBL_DCUSR0 (PUBL_REG_BASE+0x36*4) // R - DCU Status Register 0
249 #define PUBL_DCUSR1 (PUBL_REG_BASE+0x37*4) // R - DCU Status Register 1
250 #define PUBL_BISTRR (PUBL_REG_BASE+0x40*4) // R/W - BIST Run Register
251 #define PUBL_BISTMSKR0 (PUBL_REG_BASE+0x41*4) // R/W - BIST Mask Register 0
252 #define PUBL_BISTMSKR1 (PUBL_REG_BASE+0x42*4) // R/W - BIST Mask Register 1
253 #define PUBL_BISTWCR (PUBL_REG_BASE+0x43*4) // R/W - BIST Word Count Register
254 #define PUBL_BISTLSR (PUBL_REG_BASE+0x44*4) // R/W - BIST LFSR Seed Register
255 #define PUBL_BISTAR0 (PUBL_REG_BASE+0x45*4) // R/W - BIST Address Register 0
256 #define PUBL_BISTAR1 (PUBL_REG_BASE+0x46*4) // R/W - BIST Address Register 1
257 #define PUBL_BISTAR2 (PUBL_REG_BASE+0x47*4) // R/W - BIST Address Register 2
258 #define PUBL_BISTUDPR (PUBL_REG_BASE+0x48*4) // R/W - BIST User Data Pattern Register
259 #define PUBL_BISTGSR (PUBL_REG_BASE+0x49*4) // R - BIST General Status Register
260 #define PUBL_BISTWER (PUBL_REG_BASE+0x4A*4) // R - BIST Word Error Register
261 #define PUBL_BISTBER0 (PUBL_REG_BASE+0x4B*4) // R - BIST Bit Error Register 0
262 #define PUBL_BISTBER1 (PUBL_REG_BASE+0x4C*4) // R - BIST Bit Error Register 1
263 #define PUBL_BISTBER2 (PUBL_REG_BASE+0x4D*4) // R - BIST Bit Error Register 2
264 #define PUBL_BISTWCSR (PUBL_REG_BASE+0x4E*4) // R - BIST Word Count Status Register
265 #define PUBL_BISTFWR0 (PUBL_REG_BASE+0x4F*4) // R - BIST Fail Word Register 0
266 #define PUBL_BISTFWR1 (PUBL_REG_BASE+0x50*4) // R - BIST Fail Word Register 1
267 #define PUBL_ZQ0CR0 (PUBL_REG_BASE+0x60*4) // R/W - ZQ 0 Impedance Control Register 0
268 #define PUBL_ZQ0CR1 (PUBL_REG_BASE+0x61*4) // R/W - ZQ 0 Impedance Control Register 1
269 #define PUBL_ZQ0SR0 (PUBL_REG_BASE+0x62*4) // R - ZQ 0 Impedance Status Register 0
270 #define PUBL_ZQ0SR1 (PUBL_REG_BASE+0x63*4) // R - ZQ 0 Impedance Status Register 1
271 #define PUBL_ZQ1CR0 (PUBL_REG_BASE+0x64*4) // R/W - ZQ 1 Impedance Control Register 0
272 #define PUBL_ZQ1CR1 (PUBL_REG_BASE+0x65*4) // R/W - ZQ 1 Impedance Control Register 1
273 #define PUBL_ZQ1SR0 (PUBL_REG_BASE+0x66*4) // R - ZQ 1 Impedance Status Register 0
274 #define PUBL_ZQ1SR1 (PUBL_REG_BASE+0x67*4) // R - ZQ 1 Impedance Status Register 1
275 #define PUBL_ZQ2CR0 (PUBL_REG_BASE+0x68*4) // R/W - ZQ 2 Impedance Control Register 0
276 #define PUBL_ZQ2CR1 (PUBL_REG_BASE+0x69*4) // R/W - ZQ 2 Impedance Control Register 1
277 #define PUBL_ZQ2SR0 (PUBL_REG_BASE+0x6A*4) // R - ZQ 2 Impedance Status Register 0
278 #define PUBL_ZQ2SR1 (PUBL_REG_BASE+0x6B*4) // R - ZQ 2 Impedance Status Register 1
279 #define PUBL_ZQ3CR0 (PUBL_REG_BASE+0x6C*4) // R/W - ZQ 3 Impedance Control Register 0
280 #define PUBL_ZQ3CR1 (PUBL_REG_BASE+0x6D*4) // R/W - ZQ 3 Impedance Control Register 1
281 #define PUBL_ZQ3SR0 (PUBL_REG_BASE+0x6E*4) // R - ZQ 3 Impedance Status Register 0
282 #define PUBL_ZQ3SR1 (PUBL_REG_BASE+0x6F*4) // R - ZQ 3 Impedance Status Register 1
283 #define PUBL_DX0GCR (PUBL_REG_BASE+0x70*4) // R/W - DATX8 0 General Configuration Register
284 #define PUBL_DX0GSR0 (PUBL_REG_BASE+0x71*4) // R - DATX8 0 General Status Register
285 #define PUBL_DX0GSR1 (PUBL_REG_BASE+0x72*4) // R - DATX8 0 General Status Register 1
286 #define PUBL_DX0DLLCR (PUBL_REG_BASE+0x73*4) // R - DATX8 0 DLL Control Register
287 #define PUBL_DX0DQTR (PUBL_REG_BASE+0x74*4) // R/W - DATX8 0 DQ Timing Register
288 #define PUBL_DX0DQSTR (PUBL_REG_BASE+0x75*4) // R/W - DATX8 0 DQS Timing Register
289 #define PUBL_DX1GCR (PUBL_REG_BASE+0x80*4) // R - DATX8 1 General Configration Register
290 #define PUBL_DX1GSR0 (PUBL_REG_BASE+0x81*4) // R - DATX8 1 General Status Register
291 #define PUBL_DX1GSR1 (PUBL_REG_BASE+0x82*4) // R - DATX8 1 General Status Register
292 #define PUBL_DX1DLLCR (PUBL_REG_BASE+0x83*4) // R - DATX8 1 DLL Control Register
293 #define PUBL_DX1DQTR (PUBL_REG_BASE+0x84*4) // R/W - DATX8 1 DQ Timing Register
294 #define PUBL_DX1DQSTR (PUBL_REG_BASE+0x85*4) // R/W - DATX8 1 DQS Timing Register
295 #define PUBL_DX2GCR (PUBL_REG_BASE+0x90*4) // R - DATX8 2 General Configration Register
296 #define PUBL_DX2GSR0 (PUBL_REG_BASE+0x91*4) // R - DATX8 2 General Status Register
297 #define PUBL_DX2GSR1 (PUBL_REG_BASE+0x92*4) // R - DATX8 2 General Status Register
298 #define PUBL_DX2DLLCR (PUBL_REG_BASE+0x93*4) // R - DATX8 2 DLL Control Register
299 #define PUBL_DX2DQTR (PUBL_REG_BASE+0x94*4) // R/W - DATX8 2 DQ Timing Register
300 #define PUBL_DX2DQSTR (PUBL_REG_BASE+0x95*4) // R/W - DATX8 2 DQS Timing Register
301 #define PUBL_DX3GCR (PUBL_REG_BASE+0xA0*4) // R - DATX8 3 General Configration Register
302 #define PUBL_DX3GSR0 (PUBL_REG_BASE+0xA1*4) // R - DATX8 3 General Status Register
303 #define PUBL_DX3GSR1 (PUBL_REG_BASE+0xA2*4) // R - DATX8 3 General Status Register
304 #define PUBL_DX3DLLCR (PUBL_REG_BASE+0xA3*4) // R - DATX8 3 DLL Control Register
305 #define PUBL_DX3DQTR (PUBL_REG_BASE+0xA4*4) // R/W - DATX8 3 DQ Timing Register
306 #define PUBL_DX3DQSTR (PUBL_REG_BASE+0xA5*4) // R/W - DATX8 3 DQS Timing Register
307 #define PUBL_DX4GCR (PUBL_REG_BASE+0xB0*4) // R - DATX8 4 General Configration Register
308 #define PUBL_DX4GSR0 (PUBL_REG_BASE+0xB1*4) // R - DATX8 4 General Status Register
309 #define PUBL_DX4GSR1 (PUBL_REG_BASE+0xB2*4) // R - DATX8 4 General Status Register
310 #define PUBL_DX4DLLCR (PUBL_REG_BASE+0xB3*4) // R - DATX8 4 DLL Control Register
311 #define PUBL_DX4DQTR (PUBL_REG_BASE+0xB4*4) // R/W - DATX8 4 DQ Timing Register
312 #define PUBL_DX4DQSTR (PUBL_REG_BASE+0xB5*4) // R/W - DATX8 4 DQS Timing Register
313 #define PUBL_DX5GCR (PUBL_REG_BASE+0xC0*4) // R - DATX8 5 General Configration Register
314 #define PUBL_DX5GSR0 (PUBL_REG_BASE+0xC1*4) // R - DATX8 5 General Status Register
315 #define PUBL_DX5GSR1 (PUBL_REG_BASE+0xC2*4) // R - DATX8 5 General Status Register
316 #define PUBL_DX5DLLCR (PUBL_REG_BASE+0xC3*4) // R - DATX8 5 DLL Control Register
317 #define PUBL_DX5DQTR (PUBL_REG_BASE+0xC4*4) // R/W - DATX8 5 DQ Timing Register
318 #define PUBL_DX5DQSTR (PUBL_REG_BASE+0xC5*4) // R/W - DATX8 5 DQS Timing Register
319 #define PUBL_DX6GCR (PUBL_REG_BASE+0xD0*4) // R - DATX8 6 General Configration Register
320 #define PUBL_DX6GSR0 (PUBL_REG_BASE+0xD1*4) // R - DATX8 6 General Status Register
321 #define PUBL_DX6GSR1 (PUBL_REG_BASE+0xD2*4) // R - DATX8 6 General Status Register
322 #define PUBL_DX6DLLCR (PUBL_REG_BASE+0xD3*4) // R - DATX8 6 DLL Control Register
323 #define PUBL_DX6DQTR (PUBL_REG_BASE+0xD4*4) // R/W - DATX8 6 DQ Timing Register
324 #define PUBL_DX6DQSTR (PUBL_REG_BASE+0xD5*4) // R/W - DATX8 6 DQS Timing Register
325 #define PUBL_DX7GCR (PUBL_REG_BASE+0xE0*4) // R - DATX8 7 General Configration Register
326 #define PUBL_DX7GSR0 (PUBL_REG_BASE+0xE1*4) // R - DATX8 7 General Status Register
327 #define PUBL_DX7GSR1 (PUBL_REG_BASE+0xE2*4) // R - DATX8 7 General Status Register
328 #define PUBL_DX7DLLCR (PUBL_REG_BASE+0xE3*4) // R - DATX8 7 DLL Control Register
329 #define PUBL_DX7DQTR (PUBL_REG_BASE+0xE4*4) // R/W - DATX8 7 DQ Timing Register
330 #define PUBL_DX7DQSTR (PUBL_REG_BASE+0xE5*4) // R/W - DATX8 7 DQS Timing Register
331 #define PUBL_DX8GCR (PUBL_REG_BASE+0xF0*4) // R - DATX8 8 General Configration Register
332 #define PUBL_DX8GSR0 (PUBL_REG_BASE+0xF1*4) // R - DATX8 8 General Status Register
333 #define PUBL_DX8GSR1 (PUBL_REG_BASE+0xF2*4) // R - DATX8 8 General Status Register
334 #define PUBL_DX8DLLCR (PUBL_REG_BASE+0xF3*4) // R - DATX8 8 DLL Control Register
335 #define PUBL_DX8DQTR (PUBL_REG_BASE+0xF4*4) // R/W - DATX8 8 DQ Timing Register
336 #define PUBL_DX8DQSTR (PUBL_REG_BASE+0xF5*4) // R/W - DATX8 8 DQS Timing Register
339 /******************************************************************************
341 ******************************************************************************/
344 /**----------------------------------------------------------------------------*
346 **----------------------------------------------------------------------------*/
350 /**---------------------------------------------------------------------------*/