1 /******************************************************************************
2 ** File Name: uart_reg_v3.h *
5 ** Copyright: 2010 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 06/11/2010 hao.liu Create. *
13 ******************************************************************************/
14 #ifndef _UART_REG_V3_H_
15 #define _UART_REG_V3_H_
16 /*----------------------------------------------------------------------------*
18 **------------------------------------------------------------------------- */
20 /**---------------------------------------------------------------------------*
22 **--------------------------------------------------------------------------*/
27 /**---------------------------------------------------------------------------*
29 **---------------------------------------------------------------------------*/
30 #define UART_INT_STS_MASK 0xfff
31 #define UART0_INT_STS_MASK 0x7
32 #define UART1_INT_STS_MASK (0x7<<3)
33 #define UART2_INT_STS_MASK (0x7<<6)
34 #define UART3_INT_STS_MASK (0x7<<9)
36 #define UART_INT_MASK 0xfff
37 #define UART_INT_BIT_MASK 0x7
39 #define UART_FIFO_SIZE 128
41 #define US1_RX_FIFOCNT 0xff
42 #define US1_TX_FIFOCNT 0xff00
44 #define UC_RX_WATERMARK 0x7f
45 #define UC_TX_WATERMARK 0x7f00
46 //-----------------------------------------------
47 //UART0, UART1 Registers
48 //ARM_UART0_BASE 0x83000000
49 //ARM_UART1_BASE 0x84000000
50 #define ARM_UART_TXD 0x0000 //Write data to this address initiates a character transmission through tx fifo.
51 #define ARM_UART_RXD 0x0004 //Reading this register retrieves the next data byte from the rx fifo.
52 #define ARM_UART_STS0 0x0008
53 #define ARM_UART_STS1 0x000C
54 #define ARM_UART_IEN 0x0010
55 #define ARM_UART_ICLR 0x0014
56 #define ARM_UART_CTL0 0x0018
57 #define ARM_UART_CTL1 0x001C
58 #define ARM_UART_CTL2 0x0020
59 #define ARM_UART_CLKD0 0x0024
60 #define ARM_UART_CLKD1 0x0028
61 #define ARM_UART_STS2 0x002C
62 #define ARM_UART_DSP_WAIT 0x0030
63 #define UARTDSLPTMR_PERIOD 1000 //ms
64 /* uart register effective bit definition */
65 #define REG_MASK_16 0x0000ffff
66 #define UART_STS0_MASK 0x3fff
67 #define UART_STS1_MASK REG_MASK_16
68 #define UART_STS2_MASK 0x3fff
69 #define UART_IEN_MASK 0x20ff
70 #define UART_ICLR_MASK 0x20fC
71 #define UART_CKD0_MASK REG_MASK_16
72 #define UART_CKD1_MASK 0x1f
73 #define UART_CTL0_MASK 0x3fff
74 #define UART_CTL1_MASK 0xffff
76 #define UART_TRANSFER_TIME_OUT 1000 //1000 ms
78 #define UART_BREAK_DETECT_TIME 0x1
82 status (Interrupt control) Bits....
84 US_ : U(uart) + S(status) + '_' + describe.
86 #define US_RX_FULL 0x0001
87 #define US_TX_EMPTY 0x0002
88 #define US_PARITY 0x0004
89 #define US_FRAMING 0x0008
90 #define US_RXF_OVERRUN 0x0010
91 #define US_DSR_CHANGE 0x0020
92 #define US_CTS_CHANGE 0x0040
93 #define US_BREAK 0x0080
99 #define US_RXT_OUT 0x2000
103 Config(control) value
105 #define UC_PARITY_ODD 1
106 #define UC_PARITY_EVEN 0
107 #define UC_PARITY_ENABLE 0x2
109 #define UC_SEND_BREAK 0x80
112 #define BYTE_SIZE_5 0
113 #define BYTE_SIZE_6 (1u << 2)
114 #define BYTE_SIZE_7 (2u << 2)
115 #define BYTE_SIZE_8 (3u << 2)
117 #define STOPBIT_NONE 0
118 #define STOPBIT_1 (1u << 4)
119 #define STOPBIT_1_5 (2u << 4)
120 #define STOPBIT_2 (3u << 4)
122 /* UART ctrl0 register bit definition */
123 #define UC_PARITY BIT_0
124 #define UC_BYTE_SIZE (BIT_2 | BIT_3)
125 #define UC_STOP_BIT_NUBMER (BIT_4 | BIT_5)
127 /* UART ctrl1 register bit definition */
128 #define UC_SLEFLOOP_ENABLE BIT_14
129 #define UC_DMA_ENABLE BIT_15
131 /* UART sts1 register bit position definition */
132 #define US1_RX_FIFOCNT_SHIFT 0x0
133 #define US1_TX_FIFOCNT_SHIFT 0x8
135 /* UART ctrl1 register bit position definition */
136 #define UC_PARITY_SHIFT 0x0
137 #define UC_PARITY_ENABLE_SHIFT 0x1
138 #define UC_BYTE_SIZE_SHIFT 0x2
139 #define UC_STOP_BIT_NUBMER_SHIFT 0x4
141 /* UART ctrl2 register bit position definition */
142 #define UC_RX_WATERMARK_SHIFT 0x0
143 #define UC_TX_WATERMARK_SHIFT 0x8
145 //baudrate register has 21 bits: (2exp21 - 2) / 2
146 #define BAUDRATE_MAX 2097151
148 #define RECEIVE_TIMEOUT 0x3e00
153 /* struct description */
156 /* the data that writted to this address transfer through tx fifo */
157 volatile uint32 txd; /* bit 0--7 */
158 /* read the reg retrieves the next data from the rx fifo */
159 volatile uint32 rxd; /* bit 0--7 */
161 /* interrupt status and error status, line status */
162 volatile uint32 sts0; /* bit 0--15 */
164 volatile uint32 fifo_cnt;
166 volatile uint32 ien; /* uart int enable */
167 volatile uint32 iclr; /* uart int clear */
169 volatile uint32 ctl; /* control 0 */
170 volatile uint32 flow_ctl; /* control 1 */
172 volatile uint32 watermark;
175 volatile uint32 clk0; /* Bit 0--15 */
176 volatile uint32 clk1; /* Bit 0--4 */
177 volatile uint32 masked_sts;
180 /**----------------------------------------------------------------------------*
181 ** Local Function Prototype **
182 **----------------------------------------------------------------------------*/
184 /**----------------------------------------------------------------------------*
185 ** Function Prototype **
186 **----------------------------------------------------------------------------*/
189 /**----------------------------------------------------------------------------*
191 **----------------------------------------------------------------------------*/
196 /**---------------------------------------------------------------------------*/
197 #endif //_UART_REG_V3_H_