arch/arm/include/asm/arch-sc8830/regs_global.h

   1 #ifndef REGS_GLOBAL_H
   2 #define REGS_GLOBAL_H
   3
   4 /* arch/arm/mach-sc8800s/include/mach/regs_global.h
   5  *
   6  * Copyright (C) 2010 Spreadtrum
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18  #include <asm/arch/bits.h>
  19
  20 /*----------Global Registers----------*/
  21 #ifdef GREG_BASE
  22 #undef GREG_BASE
  23 #endif
  24 #define GREG_BASE     0x4B000000
  25
  26 #define GR_GEN0                         (GREG_BASE + 0x0008)
  27 #define GR_PCTL                         (GREG_BASE + 0x000C)
  28 #define GR_IRQ                          (GREG_BASE + 0x0010)
  29 #define GR_ICLR                         (GREG_BASE + 0x0014)
  30 #define GR_GEN1                         (GREG_BASE + 0x0018)
  31 #define GR_GEN3                         (GREG_BASE + 0x001C)
  32 //#define   GR_HWRST                        (GREG_BASE + 0x0020)
  33 #define BOOT_FLAG                       (GREG_BASE + 0x0020)   //It's called GR_HWRST in other chip define
  34 #define GR_MPLL_MN                      (GREG_BASE + 0x0024)
  35 #define GR_PIN_CTL                      (GREG_BASE + 0x0028)
  36 #define GR_GEN2                         (GREG_BASE + 0x002C)
  37 #define GR_ARM_BOOT_ADDR                (GREG_BASE + 0x0030)
  38 #define GR_STC_STATE                    (GREG_BASE + 0x0034)
  39 //reserved
  40 #define GR_BUSCLK                       (GREG_BASE + 0x0044)    ////GR_BUSCLK_ALM
  41 #define GR_ARCH_CTL                     (GREG_BASE + 0x0048)
  42 #define GR_SOFT_RST                     (GREG_BASE + 0x004C)
  43 //reserved
  44 #define GR_NFC_MEM_DLY                  (GREG_BASE + 0x0058)
  45 #define GR_CLK_DLY                      (GREG_BASE + 0x005C)
  46 #define GR_GEN4                         (GREG_BASE + 0x0060)
  47 //reserved
  48 #define GR_POWCTL0                  (GREG_BASE + 0x0068)
  49 #define GR_POWCTL1                  (GREG_BASE + 0x006C)
  50 #define GR_PLL_SCR                      (GREG_BASE + 0x0070)
  51 #define GR_CLK_EN                       (GREG_BASE + 0x0074)
  52 //reserved
  53 #define GR_CLK_GEN5                     (GREG_BASE + 0x007C)
  54 //reserved
  55 #define GR_SWRST                        GR_SOFT_RST             ////mingweiflag GR_SOFT_RST or GR_SWRST?
  56 #define GR_BUSCLK_ALM                   GR_BUSCLK
  57 #define LDO_USB_PD BIT_9
  58 /*
  59   the GEN0 register bit
  60 */
  61 //reserved
  62 #define GEN0_TIMER_EN                   BIT_2
  63 #define GEN0_SIM0_EN                    BIT_3
  64 #define GEN0_I2C_EN                     BIT_4
  65 #define GEN0_GPIO_EN                    BIT_5
  66 #define GEN0_ADI_EN                     BIT_6
  67 #define GEN0_EFUSE_EN                   BIT_7
  68 #define GEN0_KPD_EN                     BIT_8
  69 //reserved
  70 #define GEN0_MCU_DSP_RST                BIT_10
  71 #define GEN0_MCU_SOFT_RST               BIT_11
  72 #define GEN0_I2S_EN                     BIT_12
  73 #define GEN0_PIN_EN                     BIT_13
  74 #define GEN0_CCIR_MCLK_EN               BIT_14
  75 #define GEN0_EPT_EN                     BIT_15
  76 #define GEN0_SIM1_EN                    BIT_16
  77 #define GEN0_SPI_EN                     BIT_17
  78 //reserved
  79 #define GEN0_SYST_EN                    BIT_19
  80 #define GEN0_UART0_EN                   BIT_20
  81 #define GEN0_UART1_EN                   BIT_21
  82 #define GEN0_UART2_EN                   BIT_22
  83 #define GEN0_VB_EN                      BIT_23
  84 #define GEN0_GPIO_RTC_EN                BIT_24
  85 //reserved
  86 #define GEN0_KPD_RTC_EN                 BIT_26
  87 #define GEN0_SYST_RTC_EN                BIT_27
  88 #define GEN0_TMR_RTC_EN                 BIT_28
  89 //reserved
  90
  91 /*
  92   the GEN1 register bit
  93 */
  94 #define GEN1_MPLL_MN_EN                 BIT_9
  95 #define GEN1_CLK_AUX0_EN                BIT_10
  96 #define GEN1_CLK_AUX1_EN                BIT_11
  97 //reserved
  98 #define GEN1_RTC_ARCH_EN                BIT_18
  99 //reserved
 100
 101 #define  MISC0_UART1_MUX_SEL         BIT_8
 102
 103 /*
 104   the APB Soft Reset register bit
 105 */
 106 #define SWRST_I2C_RST                   BIT_0
 107 #define SWRST_KPD_RST                   BIT_1
 108 //reserved
 109 #define SWRST_SIM0_RST                  BIT_5
 110 #define SWRST_SIM1_RST                  BIT_6
 111 //reserved
 112 #define SWRST_TIMER_RST                 BIT_8
 113 //reserved
 114 #define SWRST_EPT_RST                   BIT_10
 115 #define SWRST_UART0_RST                 BIT_11
 116 #define SWRST_UART1_RST                 BIT_12
 117 #define SWRST_UART2_RST                 BIT_13
 118 #define SWRST_SPI_RST                   BIT_14
 119 //reserved
 120 #define SWRST_IIS_RST                   BIT_16
 121 //reserved
 122 #define SWRST_SYST_RST                  BIT_19
 123 #define SWRST_PINREG_RST                BIT_20
 124 #define SWRST_GPIO_RST                  BIT_21
 125 #define ADI_SOFT_RST                    BIT_22
 126 #define SWRST_VBC_RST                   BIT_23
 127 #define SWRST_PWM0_RST                  BIT_24
 128 #define SWRST_PWM1_RST                  BIT_25
 129 #define SWRST_PWM2_RST                  BIT_26
 130 #define SWRST_PWM3_RST                  BIT_27
 131 #define SWRST_EFUSE_RST                 BIT_28
 132 //reserved
 133
 134 /*
 135   the ARM VB CTRL register bit
 136 */
 137 #define ARM_VB_IIS_SEL                  BIT_0
 138 #define ARM_VB_MCLKON                   BIT_1
 139 #define ARM_VB_DA0ON                    BIT_2
 140 #define ARM_VB_DA1ON                    BIT_3
 141 #define ARM_VB_AD0ON                    BIT_4
 142 #define ARM_VB_AD1ON                    BIT_5
 143 #define ARM_VB_ANAON                    BIT_6
 144 #define ARM_VB_ACC                      BIT_7
 145
 146 #define ARM_VB_ADCON                    ARM_VB_AD0ON
 147 //reserved
 148
 149 /*
 150   the Interrupt control register bit
 151 */
 152 #define IRQ_MCU_IRQ0                    BIT_0
 153 #define IRQ_MCU_FRQ0                    BIT_1
 154 #define IRQ_MCU_IRQ1                    BIT_2
 155 #define IRQ_MCU_FRQ1                    BIT_3
 156 //reserved
 157 #define IRQ_VBCAD_IRQ                   BIT_5
 158 #define IRQ_VBCDA_IRQ                   BIT_6
 159 //reserved
 160 #define IRQ_RFT_INT                     BIT_12
 161 //reserved
 162 /*
 163   the Interrupt clear register bit
 164 */
 165 #define ICLR_DSP_IRQ0_CLR               BIT_0
 166 #define ICLR_DSP_FRQ0_CLR               BIT_1
 167 #define ICLR_DSP_IRQ1_CLR               BIT_2
 168 #define ICLR_DSP_FIQ1_CLR               BIT_3
 169 //reserved
 170 #define ICLR_VBCAD_IRQ_CLR              BIT_5
 171 #define ICLR_VBCDA_IRQ_CLR              BIT_6
 172 //reserved
 173 #define ICLR_RFT_INT_CLR                BIT_12
 174 //reserved
 175
 176 /*
 177   the Clock enable register bit
 178 */
 179
 180 #define CLK_PWM0_EN                     BIT_21
 181 #define CLK_PWM1_EN                     BIT_22
 182 #define CLK_PWM2_EN                     BIT_23
 183 #define CLK_PWM3_EN                     BIT_24
 184 #define CLK_PWM0_SEL                        BIT_25
 185 #define CLK_PWM1_SEL                        BIT_26
 186 #define CLK_PWM2_SEL                        BIT_27
 187 #define CLK_PWM3_SEL                        BIT_28
 188
 189 // POWER CTL1
 190 #define POWCTL1_CONFIG                  0x7FFFF903
 191
 192 #endif //_SC8800G_REG_GLOBAL_H_
 193 // End
 194
 195