2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
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4 * This file is dual-licensed: you can use it either under the terms
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5 * of the GPL or the X11 license, at your option. Note that this dual
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6 * licensing only applies to this file, and not this project as a
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12 * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, Power On (4)Ctrl and (5)Bit, Sleep (6)Ctrl and (7)Bit,
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13 * Voltage Trimming (8)Ctrl and (9)Bits, Calibration (10)Ctrl and (11)Bits,
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14 * Voltage (12)Default, Voltage (13)Ctrl and (14)Bits, Voltage Select (15)Count and Voltage (16)List[ ... ...]
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17 SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0,
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18 ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19),
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19 1100, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300);
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21 SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9),
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22 ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19),
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23 1000, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300);
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25 SCI_REGU_REG(vddmem, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(11), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(11), 0, 0,
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26 ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(17)|BIT(18)|BIT(19),
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27 1250, ANA_REG_GLB_DCDC_MEM_ADI, BIT(5), 2, 1200, 1250);
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29 SCI_REGU_REG(vddldo, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(12), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(12), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(12),
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30 ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(20),
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31 2400, ANA_REG_GLB_DCDC_GEN_ADI, BIT(5)|BIT(6)|BIT(7), 8, 2200, 1800, 1900, 2000, 2100, 2300, 2400, 2500);
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33 SCI_REGU_REG(vddwpa, 2, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL0, BIT(11),
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34 ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(20),
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37 SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10),
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38 ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20),
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39 0, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 2600, 2700, 2800, 2900);
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41 SCI_REGU_REG(vdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(1), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(1), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(0),
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42 ANA_REG_GLB_LDO_CAL_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(7)|BIT(17)|BIT(18)|BIT(20),
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43 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200);
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45 SCI_REGU_REG(vdd28, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(2), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(2), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(1),
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46 ANA_REG_GLB_LDO_CAL_CTRL0, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(10)|BIT(16)|BIT(18)|BIT(20),
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47 2800, ANA_REG_GLB_LDO_V_CTRL0, BIT(2)|BIT(3), 4, 2800, 3000, 2650, 1800);
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49 SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2),
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50 ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20),
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51 2500, ANA_REG_GLB_LDO_V_CTRL0, BIT(4)|BIT(5), 4, 2500, 2750, 3000, 2900);
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53 SCI_REGU_REG(vddrf0, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(4), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(4), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(3),
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54 ANA_REG_GLB_LDO_CAL_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
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55 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(6)|BIT(7), 4, 2850, 2950, 2500, 1800);
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57 SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4),
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58 ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
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59 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9), 4, 2850, 2950, 2500, 1800);
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61 SCI_REGU_REG(vddrf2, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(6), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(6), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(5),
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62 ANA_REG_GLB_LDO_CAL_CTRL1, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
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63 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(10)|BIT(11), 4, 2850, 2950, 2500, 1800);
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65 SCI_REGU_REG(vddemmcio, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(7), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(6),
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66 ANA_REG_GLB_LDO_CAL_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(7)|BIT(17)|BIT(18)|BIT(20),
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67 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(12)|BIT(13), 4, 1500, 1800, 1300, 1200);
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69 SCI_REGU_REG(vddemmccore, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(8), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(8), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(7),
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70 ANA_REG_GLB_LDO_CAL_CTRL2, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(10)|BIT(16)|BIT(18)|BIT(20),
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71 3000, ANA_REG_GLB_LDO_V_CTRL0, BIT(14)|BIT(15), 4, 2800, 3000, 2500, 1800);
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73 SCI_REGU_REG(avdd18, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(0),
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74 ANA_REG_GLB_LDO_CAL_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(7)|BIT(17)|BIT(18)|BIT(20),
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75 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200);
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77 SCI_REGU_REG(vddsd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(1),
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78 ANA_REG_GLB_LDO_CAL_CTRL3, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
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79 2800, ANA_REG_GLB_LDO_V_CTRL1, BIT(2)|BIT(3), 4, 2800, 3000, 2500, 1800);
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81 SCI_REGU_REG(vddsim0, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(2),
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82 ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20),
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83 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(4)|BIT(5), 4, 1800, 2900, 3000, 3100);
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85 SCI_REGU_REG(vddsim1, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(3),
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86 ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20),
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87 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(6)|BIT(7), 4, 1800, 2900, 3000, 3100);
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89 SCI_REGU_REG(vddsim2, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(4),
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90 ANA_REG_GLB_LDO_CAL_CTRL4, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(16)|BIT(18)|BIT(20),
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91 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9), 4, 2800, 3000, 2500, 1800);
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93 SCI_REGU_REG(vddcama, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(5),
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94 ANA_REG_GLB_LDO_CAL_CTRL4, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
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95 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1), 4, 2800, 3000, 2500, 1800);
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97 SCI_REGU_REG(vddcamd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(6),
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98 ANA_REG_GLB_LDO_CAL_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(6)|BIT(17)|BIT(18)|BIT(20),
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99 1500, ANA_REG_GLB_LDO_V_CTRL2, BIT(2)|BIT(3), 4, 1500, 1800, 1300, 1200);
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101 SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7),
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102 ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20),
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103 1800, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1500, 1800, 2500, 2800);
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105 SCI_REGU_REG(vddcammot, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(8),
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106 ANA_REG_GLB_LDO_CAL_CTRL5, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
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107 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(6)|BIT(7), 4, 3000, 3300, 2800, 1800);
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109 SCI_REGU_REG(vddusb, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(9), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(9),
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110 ANA_REG_GLB_LDO_CAL_CTRL2, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20),
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111 3300, ANA_REG_GLB_LDO_V_CTRL2, BIT(8)|BIT(9), 4, 3300, 3400, 3200, 3100);
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113 SCI_REGU_REG(vddclsg, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(10),
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114 ANA_REG_GLB_LDO_CAL_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(17)|BIT(18)|BIT(20),
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115 0, ANA_REG_GLB_LDO_V_CTRL2, BIT(10)|BIT(11), 4, 1500, 1800, 1300, 1200);
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